[Tremor] reg: 32 bit representation

[Dhanabal]

Can you please explain the phrase a little clearly "two-integer floating
point representation" . I assumed that tremor is fixed point code for 32 bit
DSP processors. I am working on a 32 bit fixed point DSP processor that does
have shifters as you have mentioned.



Thanks
Dhanabal


----- Original Message ----- 
From: "Monty" <xiphmont at xiph.org>
To: "Dhanabal" <dhanapalb at gmail.com>
Cc: <tremor at xiph.org>
Sent: Thursday, March 31, 2005 12:39 PM
Subject: Re: [Tremor] reg: 32 bit representation


>
>
>
> On Thu, Mar 31, 2005 at 12:16:57PM +0530, Dhanabal wrote:
> > In vorbis I specification 1.3.2.8 it is mentioned that 48 by 24 bit
multiplication should be taken care of. How is done in a 32 bit processor?
How does the tremor code actually handle these data?
>
> It's a 24x24->48 bit [minimum] multiply in fact.  That stage of Tremor
> is using a two-integer floating point representation for the vectors
> to be multiplied.  Several modern DSP families (such as ARM) have ALU
> input shifters to make this approach efficient.
>
> Monty