[Tremor] reg: 32 bit representation
xiphmont at xiph.org
Wed Mar 30 23:09:56 PST 2005
On Thu, Mar 31, 2005 at 12:16:57PM +0530, Dhanabal wrote:
> In vorbis I specification 126.96.36.199 it is mentioned that 48 by 24 bit multiplication should be taken care of. How is done in a 32 bit processor? How does the tremor code actually handle these data?
It's a 24x24->48 bit [minimum] multiply in fact. That stage of Tremor
is using a two-integer floating point representation for the vectors
to be multiplied. Several modern DSP families (such as ARM) have ALU
input shifters to make this approach efficient.
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