[tremor] Memory optimizations

[timmy brolin]

>>> The ipod has two arm7tdmi cores running at up to > 90MHz, so this 
>>> should be
>>> no problem. My problem is with memory bandwidth - the 32MB main 
>>> memory is
>>> connected to the CPUs on a very slow bus. But we have 96kB fast SRAM.
>>> Unoptimized ivorbisfile_example runs at about 50-80% speed depending 
>>> on bitrate.
>>
>> There is no cache? If there is... Turn it on and it will most likely 
>> solve the problem for you.

>Dunno if it has a cache, but most ARM7 caches are pathetic (small,
>non-harvard, small associativity, pseudo-random replacement, etc.)
>Segher

Yes, but even the most simplistic cache will make sure the loops run fast.
Given the performanace (90MHz) that might very well be enough. If it is not, move some buffers and a few LUTs to internal RAM and the problem should be solved.

There is 96kB internal RAM. Many ARM7 cores make it possible to choose if the internal RAM is to be used as RAM or cache. The odd size 96kB suggests that the memory consists of one 32kB area and one 64kB area. Perhaps the 32kB area can be configured as cache.

/Timmy

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