[tremor] Tremor HW (FPGA) implementation

[Jaime Andres Aranguren Cardona]

If so, what did those guys at Finearch did? Check this out!

http://www.finearch.com/english/index.htm

------------------------------
Jaime Andres Aranguren Cardona
CAC ImpSat/Conavi - Medellin
Tel: (4) 312-93-13

<p>-----Mensaje original-----
De: owner-tremor at xiph.org [mailto:owner-tremor at xiph.org]En nombre de
Brendan Moran
Enviado el: Jueves, 24 de Julio de 2003 01:19 a.m.
Para: tremor at xiph.org
Asunto: Re: [tremor] Tremor HW (FPGA) implementation

<p>Sadly, I doubt it will work.  As far as I know, I was the only person that 
ever posted anything about the idea, but IIRC no one thought it was 
feasible at all.

The main answer I got was: "The rather high memory requirements of tremor 
might be a bit of a problem for a hardware implementation. Memory is 
expensive."  Really your problem is that the memory requirement for the 
decoder is unbounded last I checked (there may be a change in that).

Sorry I couldn't be more help.

--Brendan

>I'm a professor for an FPGA based digital design class and my students
>proposed a Vorbis audio decoder as a final project (actually they
>proposed mp3, I changed it to Vorbis). We have Spartan IIe (200)
>development boards but I'm afraid we won't be able to implement the
>decoder due to lack of memory (only 56 Kbits internal memory in the
>FPGA)
>
>I've been looking through the archives and found several postings
>regarding the implementation of a HW Vorbis decoder. Has anybody been
>working on this or looked into the memory requirements for the decoder.
>
>Thanks, Guillermo Guichal

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