jkintree at swbell.net
Thu Feb 14 12:17:04 PST 2008
On Thursday 14 February 2008 06:16 am, xiphmont at xiph.org wrote:
> Could it possibly make sense? Yes, but that would depend on the
> details of the coprocessor. Do you have any specific parameters for
> the coprocessor in mind?
In March of 2005, Andrey Filippov reported that he had used a
Xilinx Spartan 3 FPGA with theora to design a network camera
that could compress the image from a 1280x1024 sensor at 30 fps.
According to the Xilinx web site, the Spartan-3E (XC3S1200E)
with 1.2M system gates can be purchased for under US$9.00
in quantites of 500K.
Those price/performance parameters were what I had in mind. It
just seems like doing the compression right behind the sensor
is the way to go. With a 640x480 sensor, maybe that kind of FPGA
could also handle the audio compression?
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