[Theora-dev] 16 bits, cast on idct function

Felipe Portavales Goldstein portavales at gmail.com
Wed May 31 20:09:58 PDT 2006

Yes, It runs very well, with a very good latency.

But I synthesized for Stratix FPGA, and it consumes about 20% of the
slices, this is because the distributed RAM.
Im using (on this first version) a RAM like an array, acessing all
time , without worry.
But, It inferrs flipflops for each memory position, and big muxes to control it.

So, to solve this problem, I will use a syncronous memory model, That
will inferr Block RAMS (FPGA specialized blocks). This is like small
SDRAMs on th FPGA chip.

I think that using it , the area can drop down to 3% to 5% of the
Stratix FPGA slices.

On 5/31/06, Ralph Giles <giles at xiph.org> wrote:
> On Wed, May 31, 2006 at 04:26:50PM -0300, Felipe Portavales Goldstein wrote:
> >
> > IDCT_SLOW VHDL model is working
> > but I neet optimize it to consume less FPGA resources like multiplyers.
> >
> > i will send to svn this night
> SWEET!!!
> This runs in ghdl?
>  -r

Felipe Portavales <portavales at gmail.com>
Undergraduate Student - IC-UNICAMP
Computer Systems Laboratory

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