[theora-dev] Idct - fpga - improved

[Felipe Portavales Goldstein]

Good news,

Working with synchrounous RAM (fpga internal SRAM blocks)  the area
usage drop from 20% to 5% of Logic Cells.
And the clock frequency from 30 Mhz to 90 Mhz.

Now I'm improving the latency of samples (number of clock cycles
needed to decode  a data sample).


Report:
--------------
Fitter Status : Successful - Mon Jun  5 16:38:21 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ
Revision Name : idctslow
Top-level Entity Name : IDctSlow
Family : Stratix II
Device : EP2S60F672C5ES
Timing Models : Final
Total ALUTs : 2,538 / 48,352 ( 5 % )
Total registers : 466
Total pins : 54 / 493 ( 11 % )
Total virtual pins : 0
Total memory bits : 3,072 / 2,544,192 ( < 1 % )
DSP block 9-bit elements : 2 / 288 ( < 1 % )
Total PLLs : 0 / 6 ( 0 % )
Total DLLs : 0 / 2 ( 0 % )









-- 
________________________________________
Felipe Portavales <portavales at gmail.com>
Undergraduate Student - IC-UNICAMP
Computer Systems Laboratory
http://www.lsc.ic.unicamp.br