[Theora-dev] FPGA implementation

Andrey Filippov theora at elphel.com
Thu Nov 18 12:57:22 PST 2004

I believe I really am on schedule, design seems to fit in the FPGA both in
resources ( will use around 65-75%) and timing. For the coding itself I
will need just Huffman encoder for the fixed-width (12-bit) "pre-tokens"
saved in the SDRAM buffer and to combine together old code for the image
acquisition, new 8-channel SDRAM controller I made earlier and the
"compressor_one" code.

Next thing - to balance registers among clock phases - too many switching
at the same time causes "ground bounce" and the chip malfunctioning due to
the high level of "noise" on ground connections. There are currently 4
signal phases (90 degrees) available and I will need to distribute modules
among them.

In parallel I need to find out the actual power consumption of the FPGA
and if the selected DC-DC converter in the camera will be sufficient - the
power required will increase when I'll have all the code running. If that
test will fail I'll have to increase the PCB size to accommodate bigger
converter - that is the reason I'm holding the camera production until
I'll resolve that matter.

In any case the board modification is rather simple and it will take me
just several days, after that I'll make a first batch of 20 cameras so
some software development can start in parallel with me continuing working
on FPGA (there are always bugs there as in the software). I'll need some
tools for testing and troubleshooting the encoder - something like single
frame analysers where I can view the data on different stages of decoding
by the standard (and tested) algorithm. I'll probably need to write some
custom tools to analyse intermediate compression data that is/will be
available in the SDRAM

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