[Speex-dev] Speex mem

Jim Crichton jim.crichton at comcast.net
Wed Oct 15 05:30:32 PDT 2008


In the source tree, the sample TI build for the C55x processor takes a little over 100K for the whole build, including program, data, and system resources (stack).  This is a narrowband-only build without the preprocessor/echo canceler or VBR support.  This size is fine on a C5509A, which has 256k bytes of RAM.  When the build is restricted to a single rate (8kbps), some code and tables can be removed, reducing the size to around 80 kbps.  Less than 30 MIPs are required for 8kbps Speex.

On the less capable C54x, the memory requirement is 20% smaller, but the MIPs requirement is >60.  As Jean-Marc said, you should be able to fit in 60 MHz, but some assembly optimization might be required.  16 Kbytes is nowhere near enough space for program and data.  If you have Flash for program and constant data storage, then you might be able to squeeze this in for a single NARROWBAND rate at the lowest complexity setting.

- Jim
  ----- Original Message ----- 
  From: Erik W. Rasmussen 
  To: speex-dev at xiph.org 
  Sent: Wednesday, October 15, 2008 2:32 AM
  Subject: [Speex-dev] Speex mem


  I need to get an overview over the memory/speed requirements for speex. We want to investigate whether we can implement on a target processor with limited resources.

  The target processor is a 16 bit fixed pint DSP with a single ALU and MAC. It runs at 60 MHz and has a total of 16 Kbytes RAM from which other processing also will eat.

  What we would like to implement is a speex encoder and decoder, both in wideband mode (16 kHz sample rate) and at a fixed rate of 28 kbps. We will not need preprocessing, echo cancelling or other add-ons,

  Has anyone got an idea as to if this will be possible.


  Erik W. Rasmussen
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  Technology Research

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