[opus] OPUS implementation with FPGA

[Fredrik Bonde]

The goal is to do a low power encoder/decoder for up to ten parallel uncorrelated Opus streams. And as you both pointed out - it would be nice to look at a simplified solution. 

Regards
Fredrik Bonde

-----Original Message-----
From: Jean-Marc Valin [mailto:jmvalin at jmvalin.ca] 
Sent: den 6 oktober 2013 01:48
To: Benjamin Schwartz
Cc: Fredrik Bonde; opus at xiph.org
Subject: Re: [opus] OPUS implementation with FPGA

Just to make sure, what's the goal here? Is the goal 1) to have a fast Opus implementation or are you 2) looking for an interesting FPGA implementation project? If 1), then an FPGA is most likely not necessary since Opus is not computationally expensive. If 2), then it depends on the desired size of the project and the desired quality. The simplest encoder possible is indeed simpler than the decoder (as Ben pointed out), but a good quality encoder for lower rates (hence SILK mode) is much more complicated than implementing the full decoder with SILK and CELT.

Cheers,

	Jean-Marc

On 10/05/2013 05:40 PM, Benjamin Schwartz wrote:
> I'm not aware of an FPGA implementations yet.  You could be the first!
> 
> An encoder implementation would be much easier, because there are 
> almost no rules about encoders.  An encoder is free to behave any way 
> it wants, so you could implement a very small subset of Opus and still 
> have a compliant (and useful) encoder.
> 
> A decoder implementation would be much harder, because decoders are 
> required to implement the entire standard, at all modes, samplerates, 
> bitrates, stereo/mono, etc.  However, an HDL implementation of a 
> decoder would be more impressive, and maybe more useful to others.
> 
> I recommend starting with an encoder.
> 
> 
> On Fri, Oct 4, 2013 at 2:15 AM, Fredrik Bonde <Fredrik.Bonde at ascom.se 
> <mailto:Fredrik.Bonde at ascom.se>> wrote:
> 
>     __ __
> 
>                     Hi,____
> 
>     __ __
> 
>     We would like to use the OPUS codec @ 16 kHz sampling rate and max
>     32 kbps. ____
> 
>     __ __
> 
>     What about implementing an OPUS coder and decoder in an FPGA? Has
>     this been done? Would either coder or decoder more suitable for FPGA
>     implementation? ____
> 
>     __ __
> 
>     Best regards____
> 
>     Fredrik Bonde____
> 
>     __ __
> 
> 
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