[xiph-commits] r13828 - in trunk/theora-fpga: . leon3 testbenchs
theora_hardware
andre.lnc at svn.xiph.org
andre.lnc at svn.xiph.org
Sat Sep 15 17:18:53 PDT 2007
Author: andre.lnc
Date: 2007-09-15 17:18:52 -0700 (Sat, 15 Sep 2007)
New Revision: 13828
Added:
trunk/theora-fpga/theora_hardware/
trunk/theora-fpga/theora_hardware/UpdateUMV.vhd
trunk/theora-fpga/theora_hardware/YCbCr2RGB.vhd
trunk/theora-fpga/theora_hardware/clamp.vhd
trunk/theora-fpga/theora_hardware/copyrecon.vhd
trunk/theora-fpga/theora_hardware/databuffer.vhd
trunk/theora-fpga/theora_hardware/divider.vhd
trunk/theora-fpga/theora_hardware/dual_syncram.vhd
trunk/theora-fpga/theora_hardware/expandblock.vhd
trunk/theora-fpga/theora_hardware/idctslow.vhd
trunk/theora-fpga/theora_hardware/interface_vga.vhd
trunk/theora-fpga/theora_hardware/lflimits.vhd
trunk/theora-fpga/theora_hardware/loopfilter.vhd
trunk/theora-fpga/theora_hardware/reconframes.vhd
trunk/theora-fpga/theora_hardware/reconpixelindex.vhd
trunk/theora-fpga/theora_hardware/reconrefframes.vhd
trunk/theora-fpga/theora_hardware/theora_hardware.vhd
trunk/theora-fpga/theora_hardware/tsyncram.vhd
Removed:
trunk/theora-fpga/leon3/quartus_config/
trunk/theora-fpga/modules/
trunk/theora-fpga/testbenchs/libtheora_tb_1.0alpha6.tar.gz
Log:
theora hardware
Deleted: trunk/theora-fpga/testbenchs/libtheora_tb_1.0alpha6.tar.gz
===================================================================
(Binary files differ)
Added: trunk/theora-fpga/theora_hardware/UpdateUMV.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/UpdateUMV.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/UpdateUMV.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,648 @@
+library std;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+--ordem this last gold
+entity UpdateUMV is
+
+ port (Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic
+ );
+end UpdateUMV;
+
+
+architecture a_UpdateUMV of UpdateUMV is
+ component ReconPixelIndex
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+ end component;
+
+
+ -- We are using 1024 as the maximum width and height size
+ -- = ceil(log2(Maximum Size))
+ constant LG_MAX_SIZE : natural := 10;
+ constant MEM_ADDR_WIDTH : natural := 20;
+
+-------------------------------------------------------------------------------
+-- Signals that must be read at the beginning
+-------------------------------------------------------------------------------
+ signal HFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal VFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal YStride : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal UVStride : unsigned(LG_MAX_SIZE downto 0);
+ signal YPlaneFragments : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal UVPlaneFragments : unsigned(LG_MAX_SIZE*2-2 downto 0);
+ signal ReconYDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconUDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconVDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal info_height : unsigned(LG_MAX_SIZE-1 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- Signal that must be read for all frames
+-------------------------------------------------------------------------------
+ signal FrameOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- ReconPixelIndex signal
+-------------------------------------------------------------------------------
+ constant RPI_DATA_WIDTH : positive := 32;
+ constant RPI_POS_WIDTH : positive := 17;
+ signal rpi_position : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal rpi_value : signed(RPI_DATA_WIDTH-1 downto 0);
+
+ signal s_rpi_in_request : std_logic;
+ signal s_rpi_in_valid : std_logic;
+ signal s_rpi_in_data : signed(31 downto 0);
+
+ signal s_rpi_out_requested : std_logic;
+ signal s_rpi_out_valid : std_logic;
+ signal s_rpi_out_data : signed(31 downto 0);
+
+-------------------------------------------------------------------------------
+-- Internal Signals
+-------------------------------------------------------------------------------
+ signal count : integer range 0 to 4095;
+ signal count2 : unsigned(4 downto 0);
+
+ -- VERIFICAR OS TIPOS
+ signal PlaneStride : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal PlaneBorderWidth : unsigned(4 downto 0);
+ signal LineFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal PlaneHeight : unsigned(LG_MAX_SIZE-1 downto 0);
+ signal BlockVStep : unsigned(LG_MAX_SIZE+5 downto 0);
+ signal PlaneFragments : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal position : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal SrcPtr1 : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal DestPtr1 : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal DestPtr1_i : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal SrcPtr2 : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal DestPtr2 : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal DestPtr2_i : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+ signal copy1 : signed(31 downto 0);
+ signal copy2 : signed(31 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- States and sub-states
+-------------------------------------------------------------------------------
+
+ type layer_t is (stt_Y, stt_U, stt_V);
+ signal layer : layer_t;
+
+ type state_t is (stt_readin, stt_Calc_RPI_Value,
+ stt_Ver, stt_Hor,
+ stt_done, stt_ReadMem,
+ stt_WriteMem);
+ signal state : state_t;
+ signal save_state : state_t;
+
+ type read_state_t is (stt_read_HFragments,
+ stt_read_YPlaneFragments,
+ stt_read_YStride,
+ stt_read_UVPlaneFragments,
+ stt_read_UVStride,
+ stt_read_VFragments,
+ stt_read_ReconYDataOffset,
+ stt_read_ReconUDataOffset,
+ stt_read_ReconVDataOffset,
+ stt_read_info,
+ stt_read_offset);
+ signal read_state : read_state_t;
+
+ type calc_rpi_state_t is (stt_calc_rpi1, stt_calc_rpi2);
+ signal calc_rpi_state : calc_rpi_state_t;
+
+ type update_state_t is (stt_1, stt_2, stt_3, stt_4, stt_5);
+ signal update_state : update_state_t;
+
+ type update_int_state_t is (stt_read1, stt_read2, stt_wait, stt_write1, stt_write2);
+ signal update_int_state : update_int_state_t;
+
+-------------------------------------------------------------------------------
+-- Constants
+-------------------------------------------------------------------------------
+
+ constant UMV_BORDER : unsigned(4 downto 0) := "10000";
+ constant HFRAGPIXELS : unsigned(3 downto 0) := "1000";
+ constant VFRAGPIXELS : unsigned(3 downto 0) := "1000";
+
+
+ signal s_in_request : std_logic;
+
+ signal s_out_done : std_logic;
+
+ signal s_in_sem_request : std_logic;
+ signal s_out_sem_valid : std_logic;
+
+-- Memories Signals
+ signal mem_rd_data : signed(31 downto 0);
+
+
+begin
+
+ in_request <= s_in_request;
+ in_sem_request <= s_in_sem_request;
+ out_sem_valid <= s_out_sem_valid;
+ out_done <= s_out_done;
+
+
+
+ rpi0: reconpixelindex
+ port map (Clk => Clk,
+ Reset_n => Reset_n,
+ in_request => s_rpi_out_requested,
+ in_valid => s_rpi_out_valid,
+ in_data => s_rpi_out_data,
+
+ out_requested => s_rpi_in_request,
+ out_valid => s_rpi_in_valid,
+ out_data => s_rpi_in_data);
+
+ RPI_HandShake: process (in_data, in_valid,
+ state, read_state,
+ calc_rpi_state,
+ rpi_position,
+ s_in_request)
+ begin -- process RPI_HandShake
+ s_rpi_out_data <= x"00000000";
+ s_rpi_out_valid <= '0';
+ if (s_in_request = '1') then
+ if (state = stt_readIn and
+ read_state /= stt_read_info and
+ read_state /= stt_read_offset) then
+ s_rpi_out_data <= in_data;
+ s_rpi_out_valid <= in_valid;
+ end if;
+ else
+ if (state = stt_Calc_RPI_Value and
+ calc_rpi_state = stt_calc_rpi1) then
+ s_rpi_out_data <= resize(signed('0'&rpi_position), 32);
+ s_rpi_out_valid <= '1';
+ end if;
+ end if;
+ end process RPI_HandShake;
+
+
+ process (clk)
+
+ procedure ReadIn is
+ begin
+ s_in_request <= '1';
+ s_out_sem_valid <= '0';
+ s_in_sem_request <= '0';
+ if (s_in_request = '1' and in_valid = '1') then
+ case read_state is
+ when stt_read_HFragments =>
+ HFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ read_state <= stt_read_YPlaneFragments;
+
+
+ when stt_read_YPlaneFragments =>
+ YPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2 downto 0));
+ read_state <= stt_read_YStride;
+
+
+ when stt_read_YStride =>
+ YStride <= unsigned(in_data(LG_MAX_SIZE+1 downto 0));
+ read_state <= stt_read_UVPlaneFragments;
+
+
+ when stt_read_UVPlaneFragments =>
+ UVPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2-2 downto 0));
+ read_state <= stt_read_UVStride;
+
+
+ when stt_read_UVStride =>
+ UVStride <= unsigned(in_data(LG_MAX_SIZE downto 0));
+ read_state <= stt_read_VFragments;
+
+
+ when stt_read_VFragments =>
+ VFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ read_state <= stt_read_ReconYDataOffset;
+
+
+ when stt_read_ReconYDataOffset =>
+ ReconYDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ read_state <= stt_read_ReconUDataOffset;
+
+
+ when stt_read_ReconUDataOffset =>
+ ReconUDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ read_state <= stt_read_ReconVDataOffset;
+
+
+ when stt_read_ReconVDataOffset =>
+ ReconVDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ read_state <= stt_read_info;
+
+
+ when stt_read_info =>
+ info_height <= unsigned(in_data(LG_MAX_SIZE-1 downto 0));
+ read_state <= stt_read_offset;
+
+
+ when others => -- when stt_offset
+ state <= stt_Ver;
+ s_in_request <= '0';
+ FrameOfs <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count2 <= "00000";
+ count <= 0;
+ end case;
+ end if;
+ end procedure ReadIn;
+
+ procedure CalcRPIValue is
+ begin
+ case calc_rpi_state is
+ when stt_calc_rpi1 =>
+ -- Wait until ReconPixelIndex can receive the data
+ if (s_rpi_out_requested = '1') then
+ calc_rpi_state <= stt_calc_rpi2;
+ end if;
+
+
+ when others =>
+ -- Wait until ReconPixelIndex returns the value
+ s_rpi_in_request <= '1';
+ if (s_rpi_in_request = '1' and s_rpi_in_valid = '1') then
+ rpi_value <= s_rpi_in_data;
+ state <= save_state;
+ end if;
+ end case;
+ end procedure CalcRPIValue;
+
+
+ procedure Vert is
+ begin
+ case update_state is
+ when stt_1 =>
+ update_state <= stt_2;
+ case layer is
+ when stt_Y =>
+ PlaneStride <= YStride;
+-- assert FrameOfs = 15360 report "LastFrame";
+-- assert FrameOfs = 7680 report "--------------------GoldFrame";
+ PlaneBorderWidth <= UMV_BORDER;
+ LineFragments <= HFragments;
+ PlaneHeight <= info_height;
+
+ rpi_position <= resize("00", RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Ver;
+
+ position <= resize("00", LG_MAX_SIZE*2+1);
+ when stt_U =>
+ PlaneStride <= '0' & UVStride;
+ PlaneBorderWidth <= SHIFT_RIGHT(UMV_BORDER, 1);
+ LineFragments <= SHIFT_RIGHT(HFragments, 1);
+ PlaneHeight <= SHIFT_RIGHT(info_height, 1);
+
+ rpi_position <= resize(YPlaneFragments, RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Ver;
+
+ position <= YPlaneFragments;
+ when others => -- when stt_V =>
+ PlaneStride <= '0' & UVStride;
+ PlaneBorderWidth <= SHIFT_RIGHT(UMV_BORDER, 1);
+ LineFragments <= SHIFT_RIGHT(HFragments, 1);
+ PlaneHeight <= SHIFT_RIGHT(info_height, 1);
+
+ rpi_position <= resize(YPlaneFragments + UVPlaneFragments, RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Ver;
+
+ position <= YPlaneFragments + UVPlaneFragments;
+ end case;
+
+ when stt_2 =>
+ update_state <= stt_3;
+ SrcPtr1 <= resize(FrameOfs + ('0' & unsigned(rpi_value)), MEM_ADDR_WIDTH);
+ DestPtr1 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) - PlaneBorderWidth, MEM_ADDR_WIDTH);
+
+ when stt_3 =>
+ update_state <= stt_4;
+
+ rpi_position <= resize(position + LineFragments - 1, RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Ver;
+
+ when stt_4 =>
+ update_state <= stt_5;
+ SrcPtr2 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) + HFRAGPIXELS - 1, MEM_ADDR_WIDTH);
+ DestPtr2 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) + HFRAGPIXELS, MEM_ADDR_WIDTH);
+ when others => -- when stt_5 =>
+ if (count = PlaneHeight) then
+ count <= 0;
+ count2 <= "00000";
+ update_state <= stt_1;
+ case layer is
+ when stt_Y =>
+ layer <= stt_U;
+ when stt_U =>
+ layer <= stt_V;
+ when others => -- when stt_V =>
+ layer <= stt_Y;
+ state <= stt_Hor;
+ end case;
+ else
+ save_state <= state;
+ case update_int_state is
+ when stt_read1 =>
+ update_int_state <= stt_read2;
+ state <= stt_ReadMem;
+ in_sem_addr <= SHIFT_RIGHT(SrcPtr1, 2);
+ s_in_sem_request <= '1';
+
+ when stt_read2 =>
+ update_int_state <= stt_wait;
+ state <= stt_ReadMem;
+ in_sem_addr <= SHIFT_RIGHT(SrcPtr2, 2);
+ s_in_sem_request <= '1';
+ copy1 <= mem_rd_data(31 downto 24) &
+ mem_rd_data(31 downto 24) &
+ mem_rd_data(31 downto 24) &
+ mem_rd_data(31 downto 24);
+
+ when stt_wait =>
+ update_int_state <= stt_write1;
+ copy2 <= mem_rd_data(7 downto 0) &
+ mem_rd_data(7 downto 0) &
+ mem_rd_data(7 downto 0) &
+ mem_rd_data(7 downto 0);
+
+ when stt_write1 =>
+ if (count2 = PlaneBorderWidth) then
+ count2 <= "00000";
+ count <= count + 1;
+ update_int_state <= stt_read1;
+ SrcPtr1 <= SrcPtr1 + PlaneStride;
+ SrcPtr2 <= SrcPtr2 + PlaneStride;
+ DestPtr1 <= DestPtr1 + PlaneStride;
+ DestPtr2 <= DestPtr2 + PlaneStride;
+ else
+ update_int_state <= stt_write2;
+ out_sem_addr <= SHIFT_RIGHT(DestPtr1 + count2, 2);
+ out_sem_data <= copy1;
+ s_out_sem_valid <= '1';
+ state <= stt_WriteMem;
+ end if;
+
+ when others => -- when stt_write2 =>
+ update_int_state <= stt_write1;
+ out_sem_addr <= SHIFT_RIGHT(DestPtr2 + count2, 2);
+ count2 <= count2 + 4;
+ out_sem_data <= copy2;
+ s_out_sem_valid <= '1';
+ state <= stt_WriteMem;
+ end case;
+ end if;
+ end case;
+ end procedure Vert;
+
+ procedure Horz is
+ begin
+ case update_state is
+ when stt_1 =>
+ update_state <= stt_2;
+ case layer is
+ when stt_Y =>
+ BlockVStep <= YStride * (VFRAGPIXELS - 1);
+ PlaneStride <= YStride;
+ PlaneBorderWidth <= UMV_BORDER;
+ PlaneFragments <= YPlaneFragments;
+ LineFragments <= HFragments;
+
+ rpi_position <= resize("00", RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Hor;
+
+
+ position <= resize("00", LG_MAX_SIZE*2+1);
+ when stt_U =>
+ BlockVStep <= ('0' & UVStride) * (VFRAGPIXELS - 1);
+ PlaneStride <= '0' & UVStride;
+ PlaneBorderWidth <= SHIFT_RIGHT(UMV_BORDER, 1) ;
+ PlaneFragments <= "00" & UVPlaneFragments;
+ LineFragments <= SHIFT_RIGHT(HFragments, 1);
+
+ rpi_position <= resize(YPlaneFragments, RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Hor;
+
+ position <= YPlaneFragments;
+ when others => -- when stt_V =>
+ BlockVStep <= ('0' & UVStride) * (VFRAGPIXELS - 1);
+ PlaneStride <= '0' & UVStride;
+ PlaneBorderWidth <= SHIFT_RIGHT(UMV_BORDER,1) ;
+ PlaneFragments <= "00" & UVPlaneFragments;
+ LineFragments <= SHIFT_RIGHT(HFragments,1);
+
+ rpi_position <= resize(YPlaneFragments + UVPlaneFragments, RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Hor;
+
+ position <= YPlaneFragments + UVPlaneFragments;
+ end case;
+ when stt_2 =>
+ update_state <= stt_3;
+ SrcPtr1 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) - PlaneBorderWidth, MEM_ADDR_WIDTH);
+ DestPtr1 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) - PlaneBorderWidth*(PlaneStride + 1), MEM_ADDR_WIDTH);
+ when stt_3 =>
+ update_state <= stt_4;
+
+ rpi_position <= resize(position + PlaneFragments - LineFragments, RPI_POS_WIDTH);
+ state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ save_state <= stt_Hor;
+
+ when stt_4 =>
+ update_state <= stt_5;
+ SrcPtr2 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) + BlockVStep - PlaneBorderWidth, MEM_ADDR_WIDTH);
+ DestPtr2 <= resize(FrameOfs + ('0' & unsigned(rpi_value)) + BlockVStep - PlaneBorderWidth + PlaneStride, MEM_ADDR_WIDTH);
+ when others => -- when stt_5 =>
+ if (count = PlaneStride) then
+ count <= 0;
+ count2 <= "00000";
+ update_state <= stt_1;
+ case layer is
+ when stt_Y =>
+ layer <= stt_U;
+ when stt_U =>
+ layer <= stt_V;
+ when others => -- when stt_V =>
+ layer <= stt_Y;
+ state <= stt_Done;
+ end case;
+ else
+ save_state <= state;
+ case update_int_state is
+ when stt_read1 =>
+ DestPtr1_i <= DestPtr1 + count;
+ DestPtr2_i <= DestPtr2 + count;
+
+ update_int_state <= stt_read2;
+ state <= stt_ReadMem;
+ in_sem_addr <= SHIFT_RIGHT(SrcPtr1, 2);
+ s_in_sem_request <= '1';
+
+ when stt_read2 =>
+ update_int_state <= stt_wait;
+ state <= stt_ReadMem;
+ in_sem_addr <= SHIFT_RIGHT(SrcPtr2, 2);
+ s_in_sem_request <= '1';
+ copy1 <= mem_rd_data;
+
+ when stt_wait =>
+ update_int_state <= stt_write1;
+ copy2 <= mem_rd_data;
+
+ when stt_write1 =>
+ if (count2 = PlaneBorderWidth) then
+ count2 <= "00000";
+ count <= count + 4;
+ update_int_state <= stt_read1;
+ SrcPtr1 <= SrcPtr1 + 4;
+ SrcPtr2 <= SrcPtr2 + 4;
+ else
+ update_int_state <= stt_write2;
+ out_sem_addr <= SHIFT_RIGHT(DestPtr1_i, 2);
+ out_sem_data <= copy1;
+ s_out_sem_valid <= '1';
+ state <= stt_WriteMem;
+ end if;
+
+ when others => -- when stt_write2 =>
+ update_int_state <= stt_write1;
+ out_sem_addr <= SHIFT_RIGHT(DestPtr2_i, 2);
+ count2 <= count2 + 1;
+ DestPtr1_i <= DestPtr1_i + PlaneStride;
+ DestPtr2_i <= DestPtr2_i + PlaneStride;
+ out_sem_data <= copy2;
+ s_out_sem_valid <= '1';
+ state <= stt_WriteMem;
+ end case;
+ end if;
+ end case;
+ end procedure Horz;
+
+ procedure Done is
+ begin
+ if (count = 0) then
+ s_out_done <= '1';
+ count <= count+1;
+ elsif (count = 1) then
+ s_out_done <= '0';
+ count <= count+1;
+ else
+ assert false report "UpdateUMV is done" severity note;
+ state <= stt_readin;
+ read_state <= stt_read_offset;
+ count <= 0;
+ end if;
+ end procedure Done;
+
+ procedure ReadMemory is
+ begin
+ s_in_sem_request <= '1';
+ if (s_in_sem_request = '1' and in_sem_valid = '1') then
+ mem_rd_data <= in_sem_data;
+ s_in_sem_request <= '0';
+ state <= save_state;
+ end if;
+ end procedure ReadMemory;
+
+
+
+ procedure WriteMemory is
+ begin
+ if (out_sem_requested = '1') then
+ s_out_sem_valid <= '0';
+ state <= save_state;
+ end if;
+ end procedure WriteMemory;
+
+
+
+ begin -- process
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ s_out_done <= '0';
+ s_in_request <= '0';
+ layer <= stt_Y;
+ read_state <= stt_read_HFragments;
+ state <= stt_readin;
+ update_int_state <= stt_read1;
+ update_state <= stt_1;
+ count <= 0;
+ count2 <= "00000";
+ s_in_sem_request <= '0';
+ s_out_sem_valid <= '0';
+ rpi_position <= '0' & x"0000";
+ s_rpi_in_request <= '0';
+ calc_rpi_state <= stt_calc_rpi1;
+
+ HFragments <= x"11";
+ VFragments <= x"00";
+ YStride <= x"000";
+ UVStride <= "000" & x"00";
+ YPlaneFragments <= '0' & x"00000";
+ UVPlaneFragments <= "000" & x"0000";
+ ReconYDataOffset <= x"00000";
+ ReconUDataOffset <= x"00000";
+ ReconVDataOffset <= x"00000";
+ info_height <= resize("00", LG_MAX_SIZE);
+ else
+ if (Enable = '1') then
+ case state is
+ when stt_readin => ReadIn;
+ when stt_Calc_RPI_Value => CalcRPIValue;
+ when stt_Ver => Vert;
+ when stt_Hor => Horz;
+ when stt_Done => Done;
+ when stt_WriteMem => WriteMemory;
+ when stt_ReadMem => ReadMemory;
+ when others => ReadIn; state <= stt_readin;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end a_UpdateUMV;
Property changes on: trunk/theora-fpga/theora_hardware/UpdateUMV.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/YCbCr2RGB.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/YCbCr2RGB.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/YCbCr2RGB.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,719 @@
+-------------------------------------------------------------------------------
+-- Title : YCbCr to RGB converter
+-- Project : theora-fpga
+-------------------------------------------------------------------------------
+-- File : YCbCr2RGB.vhd
+-- Author : Leonardo de Paula Rosa Piga
+-- Company : LSC - IC - UNICAMP
+-- Last update: 2007/08/23
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description: A YCbCr to RGB converter
+-------------------------------------------------------------------------------
+
+
+library std;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+
+entity YCbCr2RGB is
+ generic (
+ DEPTH : natural := 8192; -- RGB MEMORY DEPTH
+ ADDR_WIDTH : natural := 13; -- RGB MEMORY ADDRESS WIDTH
+ DATA_WIDTH : natural := 24; -- RGB MEMORY DATA WIDTH
+ ZOOM : natural range 0 to 7 := 4 -- Image will be scaled to ZOOM
+ );
+ port (
+ Clk : in std_logic;
+ reset_n : in std_logic;
+
+ ---------------------------------------------------------------------------
+ -- Ports of Handshake
+ ---------------------------------------------------------------------------
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ ---------------------------------------------------------------------------
+ -- Ports of RGB frame memory
+ ---------------------------------------------------------------------------
+ rgb_rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rgb_rd_data : out signed(DATA_WIDTH-1 downto 0);
+
+ ---------------------------------------------------------------------------
+ -- Port of RGB frame memory control access
+ ---------------------------------------------------------------------------
+ can_read_mem : out std_logic
+ );
+
+
+end YCbCr2RGB;
+
+architecture a_YCbCr2RGB of YCbCr2RGB is
+
+ component tsyncram
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+ end component tsyncram;
+
+ -----------------------------------------------------------------------------
+ -- Signals of Master State Machine
+ -----------------------------------------------------------------------------
+ type state_t is (stt_clean_buffers,
+ stt_read,
+ stt_conv_readmem,
+ stt_conv_writemem
+ );
+ signal state : state_t;
+
+
+
+ -----------------------------------------------------------------------------
+ -- Signals of ReadIn procedure
+ -----------------------------------------------------------------------------
+ type read_state_t is (stt_read_height,
+ stt_read_width,
+ stt_read_Y,
+ stt_read_Cb,
+ stt_read_Cr
+ );
+ signal read_state : read_state_t;
+
+ -----------------------------------------------------------------------------
+ -- Signals of ReadMemConvert procedure
+ -----------------------------------------------------------------------------
+ type conv_readmem_state_t is (stt_conv_readmem1,
+ stt_conv_readmem2,
+ stt_conv_readmem3,
+ stt_conv_readmem4,
+ stt_conv_readmem5,
+ stt_conv_readmem6,
+ stt_conv_readmem7,
+ stt_conv_readmem8
+ );
+ signal conv_readmem_state : conv_readmem_state_t;
+
+ signal val_Y, val_Cb, val_Cr : unsigned(7 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- Signals of WriteMemConvert procedure
+ -----------------------------------------------------------------------------
+ type conv_writemem_state_t is (stt_conv_writemem1,
+ stt_conv_writemem2,
+ stt_conv_writemem3,
+ stt_conv_writemem4,
+ stt_conv_writemem5,
+ stt_conv_writemem6
+ );
+ signal conv_writemem_state : conv_writemem_state_t;
+
+ signal val_red, val_green, val_blue : signed(31 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- Signals of BufferAccessControl process
+ -----------------------------------------------------------------------------
+ type buf_access_state_t is (stt_buf_access1,
+ stt_buf_access2
+ );
+ signal buf_access_state : buf_access_state_t;
+ signal repeat_line : natural range 0 to 7;
+
+ -----------------------------------------------------------------------------
+ -- Buffer memories parameters
+ -----------------------------------------------------------------------------
+ constant MEM_Y_DEPTH : natural := 2048;
+ constant MEM_Y_DATA_WIDTH : natural := 32;
+ constant MEM_Y_ADDR_WIDTH : natural := 11;
+
+
+ constant MEM_DEPTH : natural := 512;
+ constant MEM_DATA_WIDTH : natural := 32;
+ constant MEM_ADDR_WIDTH : natural := 9;
+
+
+ constant MEM_RGB_DEPTH : natural := DEPTH;
+ constant MEM_RGB_DATA_WIDTH : natural := DATA_WIDTH;
+ constant MEM_RGB_ADDR_WIDTH : natural := ADDR_WIDTH;
+
+ constant MAX_SIZE : natural := 1023;
+ constant LG2_MAX_SIZE : natural := 10;
+ -----------------------------------------------------------------------------
+ -- signals of Y memory
+ -----------------------------------------------------------------------------
+ signal mem_Y_wr_e : std_logic;
+ signal mem_Y_wr_addr : unsigned (MEM_Y_ADDR_WIDTH-1 downto 0);
+ signal mem_Y_wr_data : signed (MEM_Y_DATA_WIDTH-1 downto 0);
+ signal mem_Y_rd_addr : unsigned (MEM_Y_ADDR_WIDTH-1 downto 0);
+ signal mem_Y_rd_data : signed (MEM_Y_DATA_WIDTH-1 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- signals of Cb memory
+ -----------------------------------------------------------------------------
+ signal mem_Cb_wr_e : std_logic;
+ signal mem_Cb_wr_addr : unsigned (MEM_ADDR_WIDTH-1 downto 0);
+ signal mem_Cb_wr_data : signed (MEM_DATA_WIDTH-1 downto 0);
+ signal mem_Cb_rd_addr : unsigned (MEM_ADDR_WIDTH-1 downto 0);
+ signal mem_Cb_rd_data : signed (MEM_DATA_WIDTH-1 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- signals of Cr memory
+ -----------------------------------------------------------------------------
+ signal mem_Cr_wr_e : std_logic;
+ signal mem_Cr_wr_addr : unsigned (MEM_ADDR_WIDTH-1 downto 0);
+ signal mem_Cr_wr_data : signed (MEM_DATA_WIDTH-1 downto 0);
+ signal mem_Cr_rd_addr : unsigned (MEM_ADDR_WIDTH-1 downto 0);
+ signal mem_Cr_rd_data : signed (MEM_DATA_WIDTH-1 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- signals of RGB memory
+ -----------------------------------------------------------------------------
+ signal mem_RGB_wr_e : std_logic;
+ signal mem_RGB_wr_addr : unsigned (MEM_RGB_ADDR_WIDTH-1 downto 0);
+ signal mem_RGB_wr_data : signed (MEM_RGB_DATA_WIDTH-1 downto 0);
+ signal mem_RGB_rd_addr : unsigned (MEM_RGB_ADDR_WIDTH-1 downto 0);
+ signal mem_RGB_rd_data : signed (MEM_RGB_DATA_WIDTH-1 downto 0);
+
+ signal mem_Y_cleaned : std_logic;
+ signal mem_Cr_cleaned : std_logic;
+ signal mem_Cb_cleaned : std_logic;
+ signal mem_RGB_cleaned : std_logic;
+
+
+ signal first_clean : std_logic;
+ signal first_write : std_logic;
+ signal half_left_half_right : std_logic; -- '0' if we will choose the left
+ -- half of Cb and Cr pixels of one
+ -- read
+
+ signal s_in_request : std_logic;
+
+ signal can_write_mem : std_logic;
+ signal new_frame : std_logic;
+
+ signal mem_read_line : integer range 0 to 1023;
+ signal mem_read_col : integer range 0 to 1023;
+ signal counter_cols, counter_lines : integer range 0 to 1023;
+
+ -----------------------------------------------------------------------------
+ -- Video parameter signals
+ -----------------------------------------------------------------------------
+ signal video_width, video_height : integer range 0 to 1023;
+
+begin -- a_YCbCr2RGB
+ mem_RGB_rd_addr <= rgb_rd_addr;
+ rgb_rd_data <= mem_RGB_rd_data;
+
+ can_read_mem <= '0' when state = stt_clean_buffers else
+ '0' when read_state = stt_read_width else
+ '0' when read_state = stt_read_height else
+ '1';
+
+ mem_Y_plane: tsyncram
+ generic map (
+ DEPTH => MEM_Y_DEPTH,
+ DATA_WIDTH => MEM_Y_DATA_WIDTH,
+ ADDR_WIDTH => MEM_Y_ADDR_WIDTH)
+ port map (
+ clk => Clk,
+ wr_e => mem_Y_wr_e,
+ wr_addr => mem_Y_wr_addr,
+ wr_data => mem_Y_wr_data,
+ rd_addr => mem_Y_rd_addr,
+ rd_data => mem_Y_rd_data);
+
+ mem_Cb_plane: tsyncram
+ generic map (
+ DEPTH => MEM_DEPTH,
+ DATA_WIDTH => MEM_DATA_WIDTH,
+ ADDR_WIDTH => MEM_ADDR_WIDTH)
+ port map (
+ clk => Clk,
+ wr_e => mem_Cb_wr_e,
+ wr_addr => mem_Cb_wr_addr,
+ wr_data => mem_Cb_wr_data,
+ rd_addr => mem_Cb_rd_addr,
+ rd_data => mem_Cb_rd_data);
+
+ mem_Cr_plane: tsyncram
+ generic map (
+ DEPTH => MEM_DEPTH,
+ DATA_WIDTH => MEM_DATA_WIDTH,
+ ADDR_WIDTH => MEM_ADDR_WIDTH)
+ port map (
+ clk => Clk,
+ wr_e => mem_Cr_wr_e,
+ wr_addr => mem_Cr_wr_addr,
+ wr_data => mem_Cr_wr_data,
+ rd_addr => mem_Cr_rd_addr,
+ rd_data => mem_Cr_rd_data);
+
+ mem_RGB: tsyncram
+ generic map (
+ DEPTH => MEM_RGB_DEPTH,
+ DATA_WIDTH => MEM_RGB_DATA_WIDTH,
+ ADDR_WIDTH => MEM_RGB_ADDR_WIDTH)
+ port map (
+ clk => Clk,
+ wr_e => mem_RGB_wr_e,
+ wr_addr => mem_RGB_wr_addr,
+ wr_data => mem_RGB_wr_data,
+ rd_addr => mem_RGB_rd_addr,
+ rd_data => mem_RGB_rd_data);
+
+
+ in_request <= s_in_request;
+
+ -- purpose: Verify if the RGB buffer was written before overwrite it
+ -- type : sequential
+ -- inputs : clk, reset_n
+ -- outputs: can_write_mem
+ BufferAccessControl: process (clk, reset_n)
+ begin -- process BufferAccessControl
+ if (reset_n) = '0' then -- asynchronous reset (active low)
+ can_write_mem <= '1';
+ buf_access_state <= stt_buf_access1;
+ repeat_line <= 0;
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+
+ case buf_access_state is
+ when stt_buf_access1 =>
+ if (new_frame = '1') then
+ buf_access_state <= stt_buf_access2;
+ can_write_mem <= '0';
+ end if;
+ when stt_buf_access2 =>
+ if (rgb_rd_addr = video_height * video_width - 1) then
+ repeat_line <= repeat_line + 1;
+ if (repeat_line = ZOOM - 1) then
+ repeat_line <= 0;
+ buf_access_state <= stt_buf_access1;
+ can_write_mem <= '1';
+ end if;
+ end if;
+ end case;
+
+ end if;
+ end process BufferAccessControl;
+
+
+
+ -- purpose: Clean buffers, read width and height once and the frame in the YUV
+ -- format and convert the Buffer to the RGB representation
+ -- type : sequential
+ -- inputs : Clk, reset_n
+ Converter: process (Clk, reset_n)
+
+ ---------------------------------------------------------------------------
+ -- Procedure that writes zero in all positions of all memories
+ ---------------------------------------------------------------------------
+ procedure CleanBuffers is
+ begin
+ mem_Y_wr_e <= '1';
+ mem_Y_wr_data <= (others => '0');
+
+ mem_Cb_wr_e <= '1';
+ mem_Cb_wr_data <= (others => '0');
+
+ mem_Cr_wr_e <= '1';
+ mem_Cr_wr_data <= (others => '0');
+
+ mem_RGB_wr_e <= '1';
+ mem_RGB_wr_data <= (others => '0');
+
+ if (first_clean = '1') then
+ first_clean <= '0';
+ mem_Y_wr_addr <= (others => '0');
+ mem_Cb_wr_addr <= (others => '0');
+ mem_Cr_wr_addr <= (others => '0');
+ mem_RGB_wr_addr <= (others => '0');
+ else
+ mem_Y_wr_addr <= mem_Y_wr_addr + 1;
+ mem_Cb_wr_addr <= mem_Cb_wr_addr + 1;
+ mem_Cr_wr_addr <= mem_Cr_wr_addr + 1;
+ mem_RGB_wr_addr <= mem_RGB_wr_addr + 1;
+ end if;
+
+ if ((mem_Y_wr_addr = MEM_Y_DEPTH - 1) or (mem_Y_cleaned = '1')) then
+ mem_Y_wr_e <= '0';
+ mem_Y_cleaned <= '1';
+ mem_Y_wr_addr <= (others => '0');
+ end if;
+
+ if ((mem_Cb_wr_addr = MEM_DEPTH - 1) or (mem_Cb_cleaned = '1')) then
+ mem_Cb_wr_e <= '0';
+ mem_Cb_cleaned <= '1';
+ mem_Cb_wr_addr <= (others => '0');
+ end if;
+
+ if ((mem_Cr_wr_addr = MEM_DEPTH - 1) or (mem_Cr_cleaned = '1')) then
+ mem_Cr_wr_e <= '0';
+ mem_Cr_cleaned <= '1';
+ mem_Cr_wr_addr <= (others => '0');
+ end if;
+
+ if ((mem_RGB_wr_addr = MEM_RGB_DEPTH - 1) or (mem_RGB_cleaned = '1')) then
+ mem_RGB_wr_e <= '0';
+ mem_RGB_cleaned <= '1';
+ mem_RGB_wr_addr <= (others => '0');
+ end if;
+
+ if (mem_Y_cleaned = '1' and mem_Cb_cleaned = '1' and
+ mem_Cr_cleaned = '1' and mem_RGB_cleaned = '1') then
+ mem_Y_cleaned <= '0';
+ mem_Cb_cleaned <= '0';
+ mem_Cr_cleaned <= '0';
+ mem_RGB_cleaned <= '0';
+ read_state <= stt_read_Y;
+ state <= stt_read;
+ end if;
+ end procedure CleanBuffers;
+
+ procedure ReadIn is
+ begin
+
+ s_in_request <= '1';
+ if (s_in_request = '1' and in_valid = '1') then
+ case read_state is
+ when stt_read_height =>
+ video_height <= to_integer(in_data);
+ read_state <= stt_read_width;
+
+ when stt_read_width =>
+ video_width <= to_integer(in_data);
+ read_state <= stt_read_Y;
+ state <= stt_clean_buffers;
+ s_in_request <= '0';
+
+ when stt_read_Y =>
+ s_in_request <= '0';
+ mem_Y_wr_e <= '1';
+ mem_Y_wr_data <= in_data;
+ mem_Y_wr_addr <= resize
+ (SHIFT_RIGHT
+ (to_unsigned(video_width*counter_lines + counter_cols, MEM_Y_ADDR_WIDTH+4)
+ , 2), MEM_Y_ADDR_WIDTH);
+
+ counter_cols <= counter_cols + 4;
+ if (counter_cols = video_width - 4) then -- if it is the last four pixels
+ counter_cols <= 0;
+ counter_lines <= counter_lines + 1;
+ if (counter_lines = video_height - 1) then
+ counter_lines <= 0;
+ read_state <= stt_read_Cb;
+ end if;
+ end if;
+
+ when stt_read_Cb =>
+ s_in_request <= '0';
+ mem_Cb_wr_e <= '1';
+ mem_Cb_wr_data <= in_data;
+ mem_Cb_wr_addr <= resize
+ (SHIFT_RIGHT
+ (to_unsigned((video_width/2)*counter_lines + counter_cols, MEM_ADDR_WIDTH+4)
+ , 2), MEM_ADDR_WIDTH);
+
+
+ counter_cols <= counter_cols + 4;
+ if (counter_cols = to_integer(SHIFT_RIGHT(to_unsigned(video_width, LG2_MAX_SIZE), 1)) - 4) then -- if it is the last four pixels
+ counter_cols <= 0;
+ counter_lines <= counter_lines + 1;
+ if (counter_lines = (to_integer(SHIFT_RIGHT(to_unsigned(video_height, LG2_MAX_SIZE), 1))- 1)) then
+ counter_lines <= 0;
+ read_state <= stt_read_Cr;
+ end if;
+ end if;
+
+
+ when stt_read_Cr =>
+ s_in_request <= '0';
+ mem_Cr_wr_e <= '1';
+ mem_Cr_wr_data <= in_data;
+ mem_Cr_wr_addr <= resize
+ (SHIFT_RIGHT
+ (to_unsigned((video_width/2)*counter_lines + counter_cols, MEM_ADDR_WIDTH+4)
+ , 2), MEM_ADDR_WIDTH);
+
+
+ counter_cols <= counter_cols + 4;
+ if (counter_cols = to_integer(SHIFT_RIGHT(to_unsigned(video_width, LG2_MAX_SIZE), 1)) - 4) then -- if it is the last four pixels
+ counter_cols <= 0;
+ counter_lines <= counter_lines + 1;
+ if (counter_lines = (to_integer(SHIFT_RIGHT(to_unsigned(video_height, LG2_MAX_SIZE), 1))- 1)) then
+
+
+ counter_lines <= 0;
+ read_state <= stt_read_Y;
+ s_in_request <= '0';
+ state <= stt_conv_readmem;
+ conv_readmem_state <= stt_conv_readmem1;
+ end if;
+
+ end if;
+ end case;
+ end if;
+ end procedure ReadIn;
+
+ -- purpose: Read the Y, Cb and Cr memory and move to stt_conv_writedmem
+ procedure ReadMemConvert is
+ variable v_addr_Y, v_addr_CbCr : unsigned(19 downto 0);
+ begin -- ReadMemConvert
+ if (can_write_mem = '1') then -- If the frame has benn already displayed
+ case conv_readmem_state is
+ when stt_conv_readmem1 =>
+ v_addr_Y := to_unsigned(mem_read_line * video_width + mem_read_col, 20);
+ v_addr_CbCr := resize(SHIFT_RIGHT(to_unsigned(mem_read_line, 10), 1) *
+ SHIFT_RIGHT(to_unsigned(video_width, 10), 1) +
+ SHIFT_RIGHT(to_unsigned(mem_read_col, 10), 1), 20);
+
+ mem_Y_rd_addr <= resize(SHIFT_RIGHT(v_addr_Y, 2), MEM_Y_ADDR_WIDTH);
+ mem_Cb_rd_addr <= resize(SHIFT_RIGHT(v_addr_CbCr, 2), MEM_ADDR_WIDTH);
+ mem_Cr_rd_addr <= resize(SHIFT_RIGHT(v_addr_CbCr, 2), MEM_ADDR_WIDTH);
+ conv_readmem_state <= stt_conv_readmem2;
+ half_left_half_right <= '0';
+ first_write <= '1';
+
+ when stt_conv_readmem2 =>
+ -- Just wait for the memory delay
+ conv_readmem_state <= stt_conv_readmem3;
+
+ when stt_conv_readmem3 =>
+ val_Y <= unsigned(mem_Y_rd_data(31 downto 24));
+ if (half_left_half_right = '0') then
+ val_Cb <= unsigned(mem_Cb_rd_data(31 downto 24));
+ val_Cr <= unsigned(mem_Cr_rd_data(31 downto 24));
+ else
+ val_Cb <= unsigned(mem_Cb_rd_data(15 downto 8));
+ val_Cr <= unsigned(mem_Cr_rd_data(15 downto 8));
+ end if;
+ -- Move to stt_conv_writemem to convert to RGB and write the memory
+ state <= stt_conv_writemem;
+ conv_writemem_state <= stt_conv_writemem1;
+
+ -- When return from stt_conv_writemem mo to the next conv_readmem_state
+ conv_readmem_state <= stt_conv_readmem4;
+
+ when stt_conv_readmem4 =>
+ val_Y <= unsigned(mem_Y_rd_data(23 downto 16));
+ if (half_left_half_right = '0') then
+ val_Cb <= unsigned(mem_Cb_rd_data(31 downto 24));
+ val_Cr <= unsigned(mem_Cr_rd_data(31 downto 24));
+ else
+ val_Cb <= unsigned(mem_Cb_rd_data(15 downto 8));
+ val_Cr <= unsigned(mem_Cr_rd_data(15 downto 8));
+ end if;
+ -- Move to stt_conv_writemem to convert to RGB and write the memory
+ first_write <= '0';
+ state <= stt_conv_writemem;
+ conv_writemem_state <= stt_conv_writemem1;
+
+ -- When return from stt_conv_writemem mo to the next conv_readmem_state
+ conv_readmem_state <= stt_conv_readmem5;
+
+
+ when stt_conv_readmem5 =>
+ val_Y <= unsigned(mem_Y_rd_data(15 downto 8));
+ if (half_left_half_right = '0') then
+ val_Cb <= unsigned(mem_Cb_rd_data(23 downto 16));
+ val_Cr <= unsigned(mem_Cr_rd_data(23 downto 16));
+ else
+ val_Cb <= unsigned(mem_Cb_rd_data(7 downto 0));
+ val_Cr <= unsigned(mem_Cr_rd_data(7 downto 0));
+ end if;
+ -- Move to stt_conv_writemem to convert to RGB and write the memory
+ first_write <= '0';
+ state <= stt_conv_writemem;
+ conv_writemem_state <= stt_conv_writemem1;
+
+ -- When return from stt_conv_writemem mo to the next conv_readmem_state
+ conv_readmem_state <= stt_conv_readmem6;
+
+ when stt_conv_readmem6 =>
+ val_Y <= unsigned(mem_Y_rd_data(7 downto 0));
+ if (half_left_half_right = '0') then
+ val_Cb <= unsigned(mem_Cb_rd_data(23 downto 16));
+ val_Cr <= unsigned(mem_Cr_rd_data(23 downto 16));
+ else
+ val_Cb <= unsigned(mem_Cb_rd_data(7 downto 0));
+ val_Cr <= unsigned(mem_Cr_rd_data(7 downto 0));
+ end if;
+ -- Move to stt_conv_writemem to convert to RGB and write the memory
+ first_write <= '0';
+ state <= stt_conv_writemem;
+ conv_writemem_state <= stt_conv_writemem1;
+
+ -- When return from stt_conv_writemem mo to the next conv_readmem_state
+ conv_readmem_state <= stt_conv_readmem7;
+
+
+ when stt_conv_readmem7 =>
+ half_left_half_right <= not half_left_half_right;
+
+ -- Prepare to request another address
+ conv_readmem_state <= stt_conv_readmem8;
+
+ mem_read_col <= mem_read_col + 4;
+ if (mem_read_col = video_width - 4) then -- if it is the last pixel
+ mem_read_col <= 0;
+ mem_read_line <= mem_read_line + 1;
+
+ if (mem_read_line = video_height - 1) then
+ mem_read_line <= 0;
+
+ -- Convertion done
+ assert false report "YCbCr2RGB done" severity NOTE;
+ new_frame <= '1';
+ -- Can read another frame then move to read state
+ conv_readmem_state <= stt_conv_readmem1;
+ state <= stt_read;
+ read_state <= stt_read_Y;
+ end if;
+ end if;
+
+ when stt_conv_readmem8 =>
+ -- Request another address
+ v_addr_Y := to_unsigned(mem_read_line * video_width + mem_read_col, 20);
+ v_addr_CbCr := resize(SHIFT_RIGHT(to_unsigned(mem_read_line, 10), 1) *
+ SHIFT_RIGHT(to_unsigned(video_width, 10), 1) +
+ SHIFT_RIGHT(to_unsigned(mem_read_col, 10), 1), 20);
+
+ mem_Y_rd_addr <= resize(SHIFT_RIGHT(v_addr_Y, 2), MEM_Y_ADDR_WIDTH);
+ mem_Cb_rd_addr <= resize(SHIFT_RIGHT(v_addr_CbCr, 2), MEM_ADDR_WIDTH);
+ mem_Cr_rd_addr <= resize(SHIFT_RIGHT(v_addr_CbCr, 2), MEM_ADDR_WIDTH);
+ conv_readmem_state <= stt_conv_readmem2;
+ end case;
+ end if;
+ end ReadMemConvert;
+
+ -- purpose: Do YCbCr convertion and write data to the memory
+ procedure WriteMemConvert is
+ begin -- WriteMemConvert
+ case conv_writemem_state is
+ when stt_conv_writemem1 =>
+ val_red <= resize(to_signed(1220542, 22) * (signed('0' & val_Y) - 16), 32);
+ val_green <= resize(to_signed(1220542, 22) * (signed('0' &val_Y) - 16), 32);
+ val_blue <= resize(to_signed(1220542, 22) * (signed('0' &val_Y) - 16), 32);
+ conv_writemem_state <= stt_conv_writemem2;
+
+ when stt_conv_writemem2 =>
+ val_red <= val_red + to_signed(1673527, 22) * (signed('0' & val_Cr) - 128);
+ val_green <= val_green - to_signed(852492, 22) * (signed('0' &val_Cr) - 128);
+ val_blue <= val_blue + to_signed(2114978, 23) * (signed('0' &val_Cb) - 128);
+ conv_writemem_state <= stt_conv_writemem3;
+
+ when stt_conv_writemem3 =>
+ val_green <= val_green - to_signed(411042, 22) *(signed('0' &val_Cb) - 128);
+ conv_writemem_state <= stt_conv_writemem4;
+
+
+ when stt_conv_writemem4 =>
+ val_red <= SHIFT_RIGHT(val_red , 20);
+ val_green <= SHIFT_RIGHT(val_green , 20);
+ val_blue <= SHIFT_RIGHT(val_blue , 20);
+ conv_writemem_state <= stt_conv_writemem5;
+
+
+ when stt_conv_writemem5 =>
+ -- Clamp values
+ if (val_red < 0) then
+ val_red(7 downto 0) <= x"00";
+ elsif (val_red > 255) then
+ val_red(7 downto 0) <= x"ff";
+ end if;
+
+ if (val_green < 0) then
+ val_green(7 downto 0) <= x"00";
+ elsif (val_green > 255) then
+ val_green(7 downto 0) <= x"ff";
+ end if;
+
+ if (val_blue < 0) then
+ val_blue(7 downto 0) <= x"00";
+ elsif (val_blue > 255) then
+ val_blue(7 downto 0) <= x"ff";
+ end if;
+ conv_writemem_state <= stt_conv_writemem6;
+
+ when stt_conv_writemem6 =>
+ -- Write data
+ mem_RGB_wr_e <= '1';
+ mem_RGB_wr_data <= val_red(7 downto 0) & val_green(7 downto 0) & val_blue(7 downto 0);
+
+ if (first_write = '1') then
+ mem_RGB_wr_addr <= (others => '0');
+ else
+ mem_RGB_wr_addr <= mem_RGB_wr_addr + 1;
+ if (mem_RGB_wr_addr = video_height * video_width - 1) then
+ mem_RGB_wr_addr <= (others => '0');
+ end if;
+ end if;
+
+ conv_writemem_state <= stt_conv_writemem1;
+ state <= stt_conv_readmem;
+ end case;
+ end WriteMemConvert;
+
+ begin -- process Converter
+ if reset_n = '0' then -- asynchronous reset (active low)
+ state <= stt_read;
+ conv_readmem_state <= stt_conv_readmem1;
+ read_state <= stt_read_height;
+
+ mem_Y_wr_e <= '0';
+ mem_Y_wr_addr <= (others => '0');
+ mem_Y_wr_data <= (others => '0');
+ mem_Y_rd_addr <= (others => '0');
+ mem_Y_cleaned <= '0';
+
+ mem_Cb_wr_e <= '0';
+ mem_Cb_wr_addr <= (others => '0');
+ mem_Cb_wr_data <= (others => '0');
+ mem_Cb_rd_addr <= (others => '0');
+ mem_Cb_cleaned <= '0';
+
+ mem_Cr_wr_e <= '0';
+ mem_Cr_wr_addr <= (others => '0');
+ mem_Cr_wr_data <= (others => '0');
+ mem_Cr_rd_addr <= (others => '0');
+ mem_Cr_cleaned <= '0';
+
+ mem_RGB_wr_e <= '0';
+ mem_RGB_wr_addr <= (others => '0');
+ mem_RGB_wr_data <= (others => '0');
+ mem_RGB_cleaned <= '0';
+
+ first_clean <= '1';
+ half_left_half_right <= '0';
+
+ s_in_request <= '0';
+
+ elsif Clk'event and Clk = '1' then -- rising clock edge
+ s_in_request <= '0';
+ new_frame <= '0';
+ case state is
+ when stt_clean_buffers => CleanBuffers;
+ when stt_read => ReadIn;
+ when stt_conv_readmem => ReadMemConvert;
+ when stt_conv_writemem => WriteMemConvert;
+ when others =>
+ ReadIn;
+ state <= stt_read;
+ end case;
+ end if;
+ end process Converter;
+
+end a_YCbCr2RGB;
Property changes on: trunk/theora-fpga/theora_hardware/YCbCr2RGB.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/clamp.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/clamp.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/clamp.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,29 @@
+-------------------------------------------------------------------------------
+-- Description: If x < 0 then sat receives 0.
+-- If x > 255 then sat receives 255
+-- Else sat receives the eights low-order bits.
+-------------------------------------------------------------------------------
+
+library std;
+library IEEE;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_1164.all;
+
+entity clamp is
+
+ port (
+ x : in SIGNED(16 downto 0);
+ sat : out UNSIGNED(7 downto 0));
+
+ -- purpose: saturate the number in x to an unsigned number till 255
+end clamp;
+
+architecture a_clamp of clamp is
+begin -- a_clamp
+
+ sat <= "00000000" WHEN (x < 0) ELSE
+ "11111111" WHEN (x > 255) ELSE
+ unsigned(x(7 downto 0));
+
+
+end a_clamp;
Property changes on: trunk/theora-fpga/theora_hardware/clamp.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/copyrecon.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/copyrecon.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/copyrecon.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,525 @@
+-------------------------------------------------------------------------------
+-- Description: This file implements the CopyRecon.
+-- It copies the visible fragments of the source pointer
+-- to the equivalent pointed by destination pointer.
+-------------------------------------------------------------------------------
+
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity CopyRecon is
+ port (Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic
+ );
+end entity CopyRecon;
+
+
+architecture a_copyrecon of CopyRecon is
+ component tsyncram
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+ end component;
+
+
+ component ReconPixelIndex
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+ end component;
+
+
+ -- We are using 1024 as the maximum width and height size
+ -- = ceil(log2(Maximum Size))
+ constant LG_MAX_SIZE : natural := 10;
+ constant MEM_ADDR_WIDTH : natural := 20;
+-------------------------------------------------------------------------------
+-- Signals that must be read at the beginning
+-------------------------------------------------------------------------------
+ signal HFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal VFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal YStride : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal UVStride : unsigned(LG_MAX_SIZE downto 0);
+ signal YPlaneFragments : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal UVPlaneFragments : unsigned(LG_MAX_SIZE*2-2 downto 0);
+ signal ReconYDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconUDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconVDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal UnitFragmets : unsigned(LG_MAX_SIZE*2 downto 0);
+
+-------------------------------------------------------------------------------
+-- Signal that must be read for all frames
+-------------------------------------------------------------------------------
+ signal OffSetSrcPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal OffSetDestPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- Internal Signals
+-------------------------------------------------------------------------------
+ signal count : integer range 0 to 2097151;
+
+ signal BlockCount : unsigned(2 downto 0);
+ signal SlotCount : unsigned(2 downto 0);
+
+ signal ValueCount : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal EndValue : unsigned(LG_MAX_SIZE*2 downto 0);
+
+ signal PlaneLineStep : unsigned(LG_MAX_SIZE+1 downto 0);
+
+ signal s_in_request : std_logic;
+
+ signal mem_rd_data : signed(31 downto 0);
+ signal MaxDPFCount : unsigned(LG_MAX_SIZE*2 downto 0);
+
+ signal SrcPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal DestPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- ReconPixelIndex signals and constants
+-------------------------------------------------------------------------------
+ constant RPI_DATA_WIDTH : positive := 32;
+ constant RPI_POS_WIDTH : positive := 17;
+ signal rpi_position : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal rpi_value : signed(RPI_DATA_WIDTH-1 downto 0);
+
+ signal s_rpi_in_request : std_logic;
+ signal s_rpi_in_valid : std_logic;
+ signal s_rpi_in_data : signed(31 downto 0);
+
+ signal s_rpi_out_requested : std_logic;
+ signal s_rpi_out_valid : std_logic;
+ signal s_rpi_out_data : signed(31 downto 0);
+
+
+
+-------------------------------------------------------------------------------
+-- display_fragment signals and constants
+-------------------------------------------------------------------------------
+ constant DPF_DEPTH : positive := 57;
+ constant DPF_DATA_WIDTH : positive := 32;
+ constant DPF_ADDR_WIDTH : positive := 6;
+
+ signal dpf_wr_e : std_logic;
+ signal dpf_wr_addr : unsigned(DPF_ADDR_WIDTH-1 downto 0);
+ signal dpf_wr_data : signed(DPF_DATA_WIDTH-1 downto 0);
+ signal dpf_rd_addr : unsigned(DPF_ADDR_WIDTH-1 downto 0);
+ signal dpf_rd_data : signed(DPF_DATA_WIDTH-1 downto 0);
+
+-------------------------------------------------------------------------------
+-- States and sub-states
+-------------------------------------------------------------------------------
+ type state_t is (stt_ReadIn, stt_Proc, stt_CopyBlock, stt_ReadMemory,
+ stt_WriteMemory, stt_EndProc);
+ signal state : state_t;
+
+ type read_state_t is (stt_32bitsData, stt_DispFrag,
+ stt_ReadOffset);
+ signal read_state : read_state_t;
+
+ type proc_state_t is (stt_proc1, stt_proc2, stt_proc3,
+ stt_proc4, stt_proc5, stt_proc6,
+ stt_proc7, stt_proc8, stt_proc9,
+ stt_proc10);
+ signal proc_state : proc_state_t;
+
+ type copy_block_state_t is (stt_CopyBlk1, stt_CopyBlk2, stt_CopyBlk3);
+ signal copy_block_state : copy_block_state_t;
+
+
+-------------------------------------------------------------------------------
+-- HandShake
+-------------------------------------------------------------------------------
+ signal s_in_sem_request : std_logic;
+ signal s_out_sem_valid : std_logic;
+
+begin -- a_copyrecon
+
+ in_request <= s_in_request;
+ in_sem_request <= s_in_sem_request;
+ out_sem_valid <= s_out_sem_valid;
+
+
+ mem_disp_frag: tsyncram
+ generic map (DPF_DEPTH, DPF_DATA_WIDTH, DPF_ADDR_WIDTH)
+ port map (clk, dpf_wr_e, dpf_wr_addr, dpf_wr_data, dpf_rd_addr, dpf_rd_data);
+
+
+ rpi0: reconpixelindex
+ port map (Clk => Clk,
+ Reset_n => Reset_n,
+ in_request => s_rpi_out_requested,
+ in_valid => s_rpi_out_valid,
+ in_data => s_rpi_out_data,
+
+ out_requested => s_rpi_in_request,
+ out_valid => s_rpi_in_valid,
+ out_data => s_rpi_in_data);
+
+
+ RPI_HandShake: process (count, in_data, in_valid,
+ state, read_state, proc_state,
+ rpi_position, s_in_request)
+ begin -- process RPI_HandShake
+ s_rpi_out_data <= x"00000000";
+ s_rpi_out_valid <= '0';
+ if (s_in_request = '1') then
+ if (read_state = stt_32bitsData) then
+ if (count >=0 and count <=8) then
+ s_rpi_out_data <= in_data;
+ s_rpi_out_valid <= in_valid;
+ end if;
+ end if;
+ else
+ if (state = stt_Proc and
+ proc_state = stt_proc7) then
+ s_rpi_out_data <= resize(signed('0'&rpi_position), 32);
+ s_rpi_out_valid <= '1';
+ end if;
+ end if;
+ end process RPI_HandShake;
+
+
+
+ process (clk)
+-------------------------------------------------------------------------------
+-- Procedures called when state is readIn
+-------------------------------------------------------------------------------
+ procedure Read32bitsData is
+ begin
+ if (count = 0) then
+ HFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ count <= count + 1;
+ elsif (count = 1) then
+ YPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2 downto 0));
+ count <= count + 1;
+ elsif (count = 2) then
+ YStride <= unsigned(in_data(LG_MAX_SIZE+1 downto 0));
+ count <= count + 1;
+ elsif (count = 3) then
+ UVPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2-2 downto 0));
+ count <= count + 1;
+ elsif (count = 4) then
+ UVStride <= unsigned(in_data(LG_MAX_SIZE downto 0));
+ count <= count + 1;
+ elsif (count = 5) then
+ VFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ count <= count + 1;
+ elsif (count = 6) then
+ ReconYDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ elsif (count = 7) then
+ ReconUDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ elsif (count = 8) then
+ ReconVDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ else
+ UnitFragmets <= unsigned(in_data(LG_MAX_SIZE*2 downto 0));
+
+ MaxDPFCount <= SHIFT_RIGHT(
+ unsigned(in_data(LG_MAX_SIZE*2 downto 0)), 5) + 1;
+ if (in_data(4 downto 0) = "00000") then
+ MaxDPFCount <= SHIFT_RIGHT(
+ unsigned(in_data(LG_MAX_SIZE*2 downto 0)), 5);
+ end if;
+ read_state <= stt_DispFrag;
+ count <= 0;
+ end if;
+ end procedure Read32bitsData;
+
+ procedure ReadDispFrag is
+ begin
+-- assert false report "DispFrag Count = "&integer'image(count) severity note;
+ dpf_wr_e <= '1';
+ dpf_wr_data <= in_data;
+ dpf_wr_addr <= dpf_wr_addr + 1;
+ if (count = 0) then
+ dpf_wr_addr <= "000000";
+ count <= 1;
+ elsif (count = MaxDPFCount - 1) then
+ read_state <= stt_ReadOffset;
+ count <= 0;
+ else
+ count <= count + 1;
+ end if;
+ end procedure ReadDispFrag;
+
+
+ procedure ReadOffsets is
+ begin
+ dpf_wr_e <= '0';
+ if (count = 0) then
+ OffSetSrcPtr <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ else
+ s_in_request <= '0';
+ OffSetDestPtr <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= 0;
+ state <= stt_Proc;
+ read_state <= stt_DispFrag;
+ end if;
+ end procedure ReadOffsets;
+
+ procedure ReadIn is
+ begin
+ s_in_request <= '1';
+ if (s_in_request = '1' and in_valid = '1') then
+ case read_state is
+ when stt_32bitsData => Read32bitsData;
+ when stt_DispFrag => ReadDispFrag;
+ when others => ReadOffsets;
+ end case;
+ end if;
+ end procedure ReadIn;
+
+
+-------------------------------------------------------------------------------
+-- Preparing the copy
+-------------------------------------------------------------------------------
+ procedure Proc is
+ begin
+-- assert false report "proc_state = "&proc_state_t'image(proc_state) severity note;
+ case proc_state is
+ when stt_proc1 =>
+ PlaneLineStep <= YStride;
+ ValueCount <= to_unsigned(0, LG_MAX_SIZE*2+1);
+ EndValue <= YPlaneFragments;
+ proc_state <= stt_proc3;
+
+
+ when stt_proc2 =>
+ PlaneLineStep <= '0' & UVStride;
+ ValueCount <= YPlaneFragments;
+ EndValue <= UnitFragmets;
+ proc_state <= stt_proc3;
+
+
+ when stt_proc3 =>
+ dpf_rd_addr <= resize(SHIFT_RIGHT(ValueCount, 5), DPF_ADDR_WIDTH);
+ proc_state <= stt_proc4;
+
+ when stt_proc4 =>
+ -- Wait for the memory access
+ proc_state <= stt_proc5;
+
+ when stt_proc5 =>
+ proc_state <= stt_proc10;
+ -- Now we have 32 display_fragments values
+ if (dpf_rd_data(31 - to_integer(ValueCount(4 downto 0))) = '1') then
+ proc_state <= stt_proc6;
+ end if;
+
+ when stt_proc6 =>
+ -- Requet the recon_pixel_index position
+ rpi_position <= resize(ValueCount, RPI_POS_WIDTH);
+ -- Wait for the memory access
+ proc_state <= stt_proc7;
+
+ when stt_proc7 =>
+ -- Wait until ReconPixelIndex can receive the data
+ if (s_rpi_out_requested = '1') then
+ proc_state <= stt_proc8;
+ end if;
+
+ when stt_proc8 =>
+ -- Wait until ReconPixelIndex returns the value
+ s_rpi_in_request <= '1';
+ if (s_rpi_in_request = '1' and s_rpi_in_valid = '1') then
+ rpi_value <= s_rpi_in_data;
+ s_rpi_in_request <= '0';
+ proc_state <= stt_proc9;
+ end if;
+
+
+ when stt_proc9 =>
+ -- Copying the blocks
+ SrcPtr <= OffSetSrcPtr + to_integer(rpi_value);
+ DestPtr <= OffSetDestPtr + to_integer(rpi_value);
+ state <= stt_CopyBlock;
+ proc_state <= stt_proc10;
+
+
+ when stt_proc10 =>
+ proc_state <= stt_proc5;
+-- assert false report "ValueCount = "&integer'image(to_integer(ValueCount)) severity note;
+ if (ValueCount = EndValue - 1) then
+ proc_state <= stt_proc2;
+ if (ValueCount = UnitFragmets - 1) then
+ -- All done
+ out_done <= '1';
+ state <= stt_EndProc;
+ proc_state <= stt_proc1;
+ end if;
+ elsif (ValueCount(4 downto 0) = "11111") then
+ -- If we have checked all display_fragments bits
+ -- then we need to read the next display_fragment's
+ -- memory slot
+ proc_state <= stt_proc3;
+ end if;
+ ValueCount <= ValueCount + 1;
+
+ end case;
+
+ end procedure Proc;
+
+
+-------------------------------------------------------------------------------
+-- This procedure do the main job
+-------------------------------------------------------------------------------
+ procedure CopyBlock is
+ begin
+ case copy_block_state is
+ when stt_CopyBlk1 =>
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(SrcPtr + SlotCount, 2);
+ state <= stt_ReadMemory;
+ copy_block_state <= stt_CopyBlk2;
+
+
+ when stt_CopyBlk2 =>
+ out_sem_addr <= SHIFT_RIGHT(DestPtr + SlotCount, 2);
+ out_sem_data <= mem_rd_data;
+ s_out_sem_valid <= '1';
+ state <= stt_WriteMemory;
+
+ SlotCount <= SlotCount + 4;
+ copy_block_state <= stt_CopyBlk1;
+ if (SlotCount = 4) then
+ copy_block_state <= stt_CopyBlk3;
+ SlotCount <= "000";
+ end if;
+
+
+ when stt_CopyBlk3 =>
+ SrcPtr <= SrcPtr + PlaneLineStep;
+ DestPtr <= DestPtr + PlaneLineStep;
+ BlockCount <= BlockCount + 1;
+ copy_block_state <= stt_CopyBlk1;
+ if (BlockCount = 7) then
+ BlockCount <= "000";
+ state <= stt_Proc;
+ end if;
+
+ end case;
+ end procedure CopyBlock;
+
+ procedure ReadMemory is
+ begin
+ s_in_sem_request <= '1';
+ if (s_in_sem_request = '1' and in_sem_valid = '1') then
+ mem_rd_data <= in_sem_data;
+ s_in_sem_request <= '0';
+ state <= stt_CopyBlock;
+ end if;
+ end procedure ReadMemory;
+
+
+ procedure WriteMemory is
+ begin
+ if (out_sem_requested = '1') then
+ state <= stt_CopyBlock;
+ s_out_sem_valid <= '0';
+ end if;
+ end procedure WriteMemory;
+
+-------------------------------------------------------------------------------
+-- Procedures called when state is stt_EndProc
+-------------------------------------------------------------------------------
+ procedure EndProc is
+ begin
+-- assert false report "Writing Data" severity note;
+ count <= 0;
+ out_done <= '0';
+ state <= stt_readIn;
+ end procedure EndProc;
+
+
+ begin -- process
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ state <= stt_ReadIn;
+ read_state <= stt_32bitsData;
+ proc_state <= stt_proc1;
+ copy_block_state <= stt_CopyBlk1;
+ BlockCount <= "000";
+ count <= 0;
+ SlotCount <= "000";
+
+ s_in_request <= '0';
+ s_in_request <= '0';
+ s_out_sem_valid <= '0';
+ out_done <= '0';
+
+ rpi_position <= '0' & x"0000";
+ HFragments <= x"11";
+ VFragments <= x"00";
+ YStride <= x"000";
+ UVStride <= "000" & x"00";
+ YPlaneFragments <= '0' & x"00000";
+ UVPlaneFragments <= "000" & x"0000";
+ ReconYDataOffset <= x"00000";
+ ReconUDataOffset <= x"00000";
+ ReconVDataOffset <= x"00000";
+
+ s_rpi_in_request <= '0';
+ dpf_wr_e <= '0';
+ dpf_wr_addr <= to_unsigned(0, DPF_ADDR_WIDTH);
+ dpf_wr_data <= x"00000000";
+ dpf_rd_addr <= to_unsigned(0, DPF_ADDR_WIDTH);
+ else
+ s_in_request <= '0';
+ if (Enable = '1') then
+ case state is
+ when stt_ReadIn => ReadIn;
+ when stt_Proc => Proc;
+ when stt_CopyBlock => CopyBlock;
+ when stt_ReadMemory => ReadMemory;
+ when stt_WriteMemory => WriteMemory;
+ when others => EndProc;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end a_copyrecon;
Property changes on: trunk/theora-fpga/theora_hardware/copyrecon.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/databuffer.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/databuffer.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/databuffer.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,117 @@
+-------------------------------------------------------------------------------
+-- Description: This file implements a big buffer to keep
+-- the roconstructed frames (This, Golden and Last)
+-------------------------------------------------------------------------------
+
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity DataBuffer is
+
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_addr : in unsigned(19 downto 0);
+ in_data : in signed(31 downto 0);
+
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_addr : in unsigned(19 downto 0);
+ out_data : out signed(31 downto 0)
+ );
+end DataBuffer;
+
+
+architecture a_DataBuffer of DataBuffer is
+ component tsyncram
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+ end component;
+
+
+ signal count : integer;
+-- Handshake
+ signal s_in_request : std_logic;
+ signal s_out_valid : std_logic;
+
+ constant MEM_DEPTH : natural := 16384;
+ constant MEM_DATA_WIDTH : natural := 32;
+ constant MEM_ADDR_WIDTH : natural := 20;
+
+ signal mem_wr_e : std_logic;
+ signal mem_wr_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal mem_wr_data : signed(MEM_DATA_WIDTH-1 downto 0);
+ signal mem_rd_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal mem_rd_data : signed(MEM_DATA_WIDTH-1 downto 0);
+
+begin -- a_DataBuffer
+ in_request <= s_in_request;
+ out_valid <= s_out_valid;
+
+ mem_int32: tsyncram
+ generic map (MEM_DEPTH, MEM_DATA_WIDTH, MEM_ADDR_WIDTH)
+ port map (clk, mem_wr_e, mem_wr_addr, mem_wr_data,
+ mem_rd_addr, mem_rd_data);
+
+ process (clk)
+
+ begin -- process
+
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ s_in_request <= '0';
+ s_out_valid <= '0';
+
+ count <= 0;
+--memory's signals
+ mem_wr_e <= '0';
+ mem_wr_addr <= x"00000";
+ mem_wr_data <= x"00000000";
+ mem_rd_addr <= x"00000";
+ else
+
+ s_out_valid <= '0';
+ s_in_request <= '1';
+ mem_wr_e <= '0';
+ if (s_in_request = '1' and in_valid = '1') then
+ mem_wr_e <= '1';
+ mem_wr_data <= in_data;
+ mem_wr_addr <= in_addr;
+ end if;
+ count <= 0;
+ if (out_requested = '1' and s_out_valid = '0') then
+ if (count = 0) then
+ mem_rd_addr <= out_addr;
+ count <= count + 1;
+ elsif (count = 1) then
+ count <= count + 1;
+ else
+ out_data <= mem_rd_data;
+ s_out_valid <= '1';
+ count <= 0;
+ end if;
+ end if;
+ end if;
+ end if;
+ end process;
+
+end a_DataBuffer;
Property changes on: trunk/theora-fpga/theora_hardware/databuffer.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/divider.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/divider.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/divider.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,113 @@
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+
+entity divider is
+ generic (
+ WIDTH : positive := 32);
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ dividend : in unsigned(WIDTH-1 downto 0);
+ divisor : in unsigned(WIDTH-1 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ quotient : out unsigned(WIDTH-1 downto 0);
+ remainder : out unsigned(WIDTH-1 downto 0)
+ );
+end entity divider;
+
+architecture a_divider of divider is
+ type state_t is (stt_readIn, stt_divide, stt_writeOut);
+ signal state : state_t;
+
+
+ signal s_divisor : unsigned(WIDTH*2-1 downto 0);
+ signal s_quotient : unsigned(WIDTH-1 downto 0);
+ signal s_remainder : unsigned(WIDTH*2-1 downto 0);
+
+ signal s_in_request : std_logic;
+ signal s_out_valid : std_logic;
+ signal s_repetition : integer range 0 to WIDTH+1;
+
+begin -- a_divider
+
+ in_request <= s_in_request;
+ out_valid <= s_out_valid;
+
+ process (clk)
+
+ procedure ReadIn is
+ begin
+ s_out_valid <= '0'; -- came from WriteOut, out_valid must be 0
+ s_in_request <= '1';
+ if( s_in_request = '1' and in_valid = '1' )then
+ s_remainder <= resize("00", WIDTH) & dividend;
+ s_divisor <= divisor & resize("00", WIDTH);
+ s_quotient <= resize("00", WIDTH);
+ s_repetition <= 0;
+ s_in_request <= '0';
+ state <= stt_divide;
+ end if;
+ end procedure ReadIn;
+
+ procedure Divide is
+ variable v_subtractor : unsigned(WIDTH*2-1 downto 0);
+ begin
+ v_subtractor := s_remainder - s_divisor;
+
+ s_divisor <= SHIFT_RIGHT(s_divisor, 1);
+ s_quotient <= SHIFT_LEFT(s_quotient, 1);
+ if (v_subtractor(WIDTH*2-1) = '0') then -- positive
+ s_quotient(0) <= '1';
+ s_remainder <= v_subtractor;
+ else
+ s_quotient(0) <= '0';
+ end if;
+ s_repetition <= s_repetition + 1;
+ if (s_repetition = WIDTH) then
+ state <= stt_writeOut;
+ s_repetition <= 0;
+ end if;
+ end procedure Divide;
+
+
+ procedure WriteOut is
+ begin
+ s_out_valid <= '1';
+ quotient <= s_quotient;
+ remainder <= s_remainder(WIDTH-1 downto 0);
+ if (out_requested = '1') then
+ state <= stt_readIn;
+ end if;
+ end procedure WriteOut;
+
+ begin
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ s_in_request <= '0';
+ s_out_valid <= '0';
+
+ s_repetition <= 0;
+ state <= stt_readIn;
+
+ else
+ case state is
+ when stt_readIn => ReadIn;
+ when stt_divide => Divide;
+ when stt_writeOut => WriteOut;
+ when others => ReadIn; state <= stt_readIn;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end a_divider;
Property changes on: trunk/theora-fpga/theora_hardware/divider.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/dual_syncram.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/dual_syncram.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/dual_syncram.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,49 @@
+-------------------------------------------------------------------------------
+-- Description: This file implements a dual-SRAM
+-------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+
+-- This entity will infferr two identical block rams
+-- to permit two reads in the same clock cicle.
+
+entity dual_syncram is
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd1_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd1_data : out signed(DATA_WIDTH-1 downto 0);
+ rd2_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd2_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+end entity dual_syncram;
+
+architecture rtl of dual_syncram is
+
+ type MEM_TYPE is array(0 to DEPTH-1) of
+ signed(DATA_WIDTH-1 downto 0);
+ signal memory : MEM_TYPE;
+begin
+
+ process( clk )
+ begin
+ if ( rising_edge(clk) ) then
+ if ( wr_e = '1' ) then
+ memory( to_integer(wr_addr) ) <= wr_data;
+ end if;
+ rd1_data <= memory( to_integer(rd1_addr) );
+ rd2_data <= memory( to_integer(rd2_addr) );
+ end if;
+ end process;
+
+end rtl;
Property changes on: trunk/theora-fpga/theora_hardware/dual_syncram.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/expandblock.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/expandblock.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/expandblock.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,1295 @@
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity ExpandBlock is
+
+ port (
+ Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ in_newframe : in std_logic;
+ out_done : out std_logic);
+
+end ExpandBlock;
+
+architecture a_ExpandBlock of ExpandBlock is
+ component tsyncram
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+ end component;
+
+ component ReconPixelIndex
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+ end component;
+
+ component clamp
+ port (
+ x : in SIGNED(16 downto 0);
+ sat : out UNSIGNED(7 downto 0));
+ end component;
+
+ component IDctSlow
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(15 downto 0);
+ in_quantmat : in signed(15 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(15 downto 0)
+ );
+ end component;
+
+ -- We are using 1024 as the maximum width and height size
+ -- = ceil(log2(Maximum Size))
+ constant LG_MAX_SIZE : natural := 10;
+ constant MEM_ADDR_WIDTH : natural := 20;
+
+-------------------------------------------------------------------------------
+-- Signals that must be read at the beginning
+-------------------------------------------------------------------------------
+-- signal HFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+-- signal VFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal YStride : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal UVStride : unsigned(LG_MAX_SIZE downto 0);
+ signal YPlaneFragments : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal UVPlaneFragments : unsigned(LG_MAX_SIZE*2-2 downto 0);
+-- signal ReconYDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+-- signal ReconUDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+-- signal ReconVDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- Signal that must be read for all frames
+-------------------------------------------------------------------------------
+ signal FragCodMeth_FragNumber : unsigned(2 downto 0);
+-- signal FragCoefEOB_FragNumber : unsigned(31 downto 0);
+ signal FragMVect_FragNumber_x : signed(31 downto 0);
+ signal FragMVect_FragNumber_y : signed(31 downto 0);
+ signal FragmentNumber : unsigned(31 downto 0);
+ signal FrameType : unsigned(7 downto 0);
+
+ signal GoldenFrameOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ThisFrameReconOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal LastFrameReconOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- Internal Signals
+-------------------------------------------------------------------------------
+ signal CodingMode : unsigned(2 downto 0);
+ signal ReconPixelsPerLine : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal MvShift : unsigned(1 downto 0);
+ signal MvModMask : unsigned(31 downto 0);
+ signal dequant_coeffs_Ofs : unsigned(8 downto 0);
+ signal MVOffset : signed(31 downto 0);
+ signal LastFrameRecPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal LastFrameRecPtr2 : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconPtr2Offset : signed(31 downto 0);
+
+ signal s_in_request : std_logic;
+
+ signal count : integer range 0 to 511;
+-------------------------------------------------------------------------------
+-- dequant_coeffs Offsets
+-------------------------------------------------------------------------------
+ constant Y_COEFFS_OFS : unsigned(8 downto 0) := "000000000";
+ constant U_COEFFS_OFS : unsigned(8 downto 0) := "001000000";
+ constant V_COEFFS_OFS : unsigned(8 downto 0) := "010000000";
+ constant INTERY_COEFFS_OFS : unsigned(8 downto 0) := "011000000";
+ constant INTERU_COEFFS_OFS : unsigned(8 downto 0) := "100000000";
+ constant INTERV_COEFFS_OFS : unsigned(8 downto 0) := "101000000";
+
+
+-------------------------------------------------------------------------------
+-- CodingMode constants
+-------------------------------------------------------------------------------
+ constant CODE_INTER_NO_MV :
+ unsigned(2 downto 0) := "000"; -- INTER prediction, (0,0) motion vector implied.
+ constant CODE_INTRA :
+ unsigned(2 downto 0) := "001"; -- INTRA i.e. no prediction.
+ constant CODE_INTER_PLUS_MV :
+ unsigned(2 downto 0) := "010"; -- INTER prediction, non zero motion vector.
+ constant CODE_INTER_LAST_MV :
+ unsigned(2 downto 0) := "011"; -- Use Last Motion vector
+ constant CODE_INTER_PRIOR_LAST :
+ unsigned(2 downto 0) := "100"; -- Prior last motion vector
+ constant CODE_USING_GOLDEN :
+ unsigned(2 downto 0) := "101"; -- 'Golden frame' prediction (no MV).
+ constant CODE_GOLDEN_MV :
+ unsigned(2 downto 0) := "110"; -- 'Golden frame' prediction plus MV.
+ constant CODE_INTER_FOURMV :
+ unsigned(2 downto 0) := "111"; -- Inter prediction 4MV per macro block.
+
+
+-------------------------------------------------------------------------------
+-- ReconPixelIndex signal
+-------------------------------------------------------------------------------
+ constant RPI_DATA_WIDTH : positive := 32;
+ constant RPI_POS_WIDTH : positive := 17;
+ signal rpi_position : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal rpi_value : signed(RPI_DATA_WIDTH-1 downto 0);
+
+ signal s_rpi_in_request : std_logic;
+ signal s_rpi_in_valid : std_logic;
+ signal s_rpi_in_data : signed(31 downto 0);
+
+ signal s_rpi_out_requested : std_logic;
+ signal s_rpi_out_valid : std_logic;
+ signal s_rpi_out_data : signed(31 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- Constants
+-------------------------------------------------------------------------------
+ constant KEY_FRAME : unsigned(7 downto 0) := "00000000";
+ type ModeUsesMC_t is array (0 to 7) of std_logic;
+ constant ModeUsesMC : ModeUsesMC_t := ('0','0','1','1','1','0','1','1');
+
+ constant ZERO_M_VECTOR : signed(31 downto 0) := x"00000000";
+
+
+-------------------------------------------------------------------------------
+-- States and sub-states
+-------------------------------------------------------------------------------
+
+ type state_t is (stt_readIn, stt_PreRecon, stt_Recon, stt_EndProc);
+ signal state : state_t;
+
+ type read_state_t is (stt_read1, stt_read_uniq_frame_data,
+ stt_read_dqc, stt_read_qtl, stt_read2);
+ signal read_state : read_state_t;
+
+ type pre_recon_state_t is (stt_PrepIDct, stt_CallIDct, stt_RecIDct,
+ stt_Calc_RPI_Value, stt_SelectRecons);
+ signal pre_recon_state : pre_recon_state_t;
+
+ type calc_rpi_state_t is (stt_calc_rpi1, stt_calc_rpi2);
+ signal calc_rpi_state : calc_rpi_state_t;
+
+
+ type select_recons_state_t is (stt_SelectRecons_1, stt_SelectRecons_2,
+ stt_SelectRecons_3, stt_SelectRecons_4,
+ stt_SelectRecons_5, stt_SelectRecons_6);
+ signal select_recons_state : select_recons_state_t;
+
+
+ type recon_state_t is (stt_Calculate_ReconIntra,
+ stt_ReadPixels,
+ stt_Calculate_ReconInter,
+ stt_Calculate_ReconInterHalf, stt_WriteOut_Recon,
+ stt_ReadMemory, stt_WriteMemory);
+ signal recon_state, gotostate, gotostate2 : recon_state_t;
+
+ type recon_calc_state_t is (stt_CalcRecon1, stt_CalcRecon2,
+ stt_CalcRecon3, stt_CalcRecon4,
+ stt_CalcRecon5, stt_CalcRecon6,
+ stt_CalcRecon7, stt_CalcRecon8);
+ signal recon_calc_state : recon_calc_state_t;
+
+
+ type read_pixel_state_t is (stt_ReadPixels1, stt_ReadPixels2,
+ stt_ReadPixels3, stt_ReadPixels4,
+ stt_ReadPixels5, stt_ReadPixels6);
+ signal read_pixel_state : read_pixel_state_t;
+
+
+ type write_recon_state_t is (stt_WriteRecon1, stt_WriteRecon2,
+ stt_WriteReconLast);
+ signal write_recon_state : write_recon_state_t;
+
+-------------------------------------------------------------------------------
+-- IDct signals
+-------------------------------------------------------------------------------
+ signal out_idct_requested : std_logic;
+ signal out_idct_valid : std_logic := '0';
+ signal out_idct_data : signed(15 downto 0);
+ signal out_idct_quantmat : signed(15 downto 0);
+
+ signal in_idct_request : std_logic := '0';
+ signal in_idct_valid : std_logic;
+ signal in_idct_data : signed(15 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- IDct's handshake signals
+ -----------------------------------------------------------------------------
+ signal s_out_idct_valid : std_logic;
+ signal s_in_idct_request : std_logic;
+
+-------------------------------------------------------------------------------
+-- Memories signals and constants
+-------------------------------------------------------------------------------
+
+ -----------------------------------------------------------------------------
+ -- Quantized list
+ -----------------------------------------------------------------------------
+ signal qtl_wr_e : std_logic;
+ signal qtl_wr_addr : unsigned(5 downto 0);
+ signal qtl_wr_data : signed(15 downto 0);
+ signal qtl_rd_addr : unsigned(5 downto 0);
+ signal qtl_rd_data : signed(15 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- Dequantizer coefficients
+ -----------------------------------------------------------------------------
+ signal dqc_wr_e : std_logic;
+ signal dqc_wr_addr : unsigned(8 downto 0);
+ signal dqc_wr_data : signed(15 downto 0);
+ signal dqc_rd_addr : unsigned(8 downto 0);
+ signal dqc_rd_data : signed(15 downto 0);
+
+ -----------------------------------------------------------------------------
+ -- Recon Data Buffer
+ -----------------------------------------------------------------------------
+ signal rdb_wr_e : std_logic;
+ signal rdb_wr_addr : unsigned(5 downto 0);
+ signal rdb_wr_data : signed(15 downto 0);
+ signal rdb_rd_addr : unsigned(5 downto 0);
+ signal rdb_rd_data : signed(15 downto 0);
+
+
+-------------------------------------------------------------------------------
+-- Reconstruct signals, constants and types
+-------------------------------------------------------------------------------
+ subtype ogg_int_17_t is signed(16 downto 0);
+ subtype ogg_int_16_t is signed(15 downto 0);
+ subtype ogg_uint_16_t is unsigned(15 downto 0);
+ subtype ogg_uint_8_t is unsigned(7 downto 0);
+ subtype ogg_int_8_t is signed(7 downto 0);
+ subtype ogg_uint_32_t is unsigned(31 downto 0);
+
+ subtype tiny_int is integer range 0 to 255;
+
+ signal sum : ogg_int_17_t;
+ signal sat : ogg_uint_8_t;
+ shared variable auxs17b : ogg_int_17_t;
+
+-- Handshake
+
+ constant dC128 : ogg_int_17_t := "00000000010000000";
+
+ signal s_in_sem_request : std_logic;
+ signal s_out_sem_valid : std_logic;
+
+ signal colcount : tiny_int := 0;
+ signal offset_RefPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal offset_RefPtr2 : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal offset_ReconPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0); --buffer
+
+ type mem_8_8bits_t is array (0 to 7) of ogg_uint_8_t;
+ signal Pixel : mem_8_8bits_t;
+ signal Pixel1 : mem_8_8bits_t;
+
+-- Memories Signals
+ signal mem_rd_data : signed(31 downto 0);
+
+begin -- a_ExpandBlock
+
+ in_request <= s_in_request;
+ in_sem_request <= s_in_sem_request;
+ out_sem_valid <= s_out_sem_valid;
+
+ clamp255_0: clamp port map (sum, sat);
+
+ syncram_384_16: tsyncram
+ generic map (DEPTH => 384, DATA_WIDTH => 16, ADDR_WIDTH => 9)
+ port map (clk, dqc_wr_e, dqc_wr_addr, dqc_wr_data,
+ dqc_rd_addr, dqc_rd_data);
+
+ syncram_64_16: tsyncram
+ generic map (DEPTH => 64, DATA_WIDTH => 16, ADDR_WIDTH => 6)
+ port map (clk, rdb_wr_e, rdb_wr_addr, rdb_wr_data,
+ rdb_rd_addr, rdb_rd_data);
+
+
+ mem_64_int16: tsyncram
+ generic map (64, 16, 6)
+ port map (clk, qtl_wr_e, qtl_wr_addr, qtl_wr_data,
+ qtl_rd_addr, qtl_rd_data);
+
+ rpi0: reconpixelindex
+ port map (Clk => Clk,
+ Reset_n => Reset_n,
+ in_request => s_rpi_out_requested,
+ in_valid => s_rpi_out_valid,
+ in_data => s_rpi_out_data,
+
+ out_requested => s_rpi_in_request,
+ out_valid => s_rpi_in_valid,
+ out_data => s_rpi_in_data);
+
+ idctslow0: IDctSlow
+ port map(clk, Reset_n,
+ out_idct_requested, out_idct_valid, out_idct_data,
+ out_idct_quantmat,
+ in_idct_request, in_idct_valid, in_idct_data);
+
+
+ in_idct_request <= s_in_idct_request;
+ out_idct_valid <= s_out_idct_valid;
+
+
+ RPI_HandShake: process (in_data, in_valid,
+ state, read_state, pre_recon_state,
+ calc_rpi_state, rpi_position,
+ s_in_request)
+ begin -- process RPI_HandShake
+ s_rpi_out_data <= x"00000000";
+ s_rpi_out_valid <= '0';
+ if (s_in_request = '1') then
+ if (state = stt_readIn and read_state = stt_read1) then
+ s_rpi_out_data <= in_data;
+ s_rpi_out_valid <= in_valid;
+ end if;
+ else
+ if (state = stt_PreRecon and
+ pre_recon_state = stt_Calc_RPI_Value and
+ calc_rpi_state = stt_calc_rpi1) then
+ s_rpi_out_data <= resize(signed('0'&rpi_position), 32);
+ s_rpi_out_valid <= '1';
+ end if;
+ end if;
+ end process RPI_HandShake;
+
+
+
+ process (clk)
+-------------------------------------------------------------------------------
+-- Procedures called when state is stt_readIn
+-------------------------------------------------------------------------------
+ ---------------------------------------------------------------------------
+ -- Select the procedure called according the read_state
+ ---------------------------------------------------------------------------
+ procedure read1 is
+ begin
+ if (count = 0) then
+-- HFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ count <= count + 1;
+ elsif (count = 1) then
+ YPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2 downto 0));
+ count <= count + 1;
+ elsif (count = 2) then
+ YStride <= unsigned(in_data(LG_MAX_SIZE+1 downto 0));
+ count <= count + 1;
+ elsif (count = 3) then
+ UVPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2-2 downto 0));
+ count <= count + 1;
+ elsif (count = 4) then
+ UVStride <= unsigned(in_data(LG_MAX_SIZE downto 0));
+ count <= count + 1;
+ elsif (count = 5) then
+-- VFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ count <= count + 1;
+ elsif (count = 6) then
+-- ReconYDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ elsif (count = 7) then
+-- ReconUDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ --elsif (count = 8) then
+ else
+-- ReconVDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= 0;
+ read_state <= stt_read_dqc;
+ end if;
+ end procedure read1;
+
+ procedure read_dqc is
+ begin
+ dqc_wr_e <= '1';
+ dqc_wr_data <= signed(in_data(15 downto 0));
+ dqc_wr_addr <= dqc_wr_addr + 1;
+
+ if (count = 0) then
+ dqc_wr_addr <= Y_COEFFS_OFS;
+ count <= count + 1;
+ elsif (count = 383) then
+ count <= 0;
+ read_state <= stt_read_uniq_frame_data;
+ else
+ count <= count + 1;
+ end if;
+ end procedure read_dqc;
+
+ ---------------------------------------------------------------------------
+ -- Procedure that read the parameters sent one time per frame
+ ---------------------------------------------------------------------------
+ procedure ReadUniqFrameData is
+ begin
+
+ count <= count + 1;
+ if (count = 0) then
+ FrameType <= unsigned(in_data(7 downto 0));
+ elsif (count = 1) then
+ GoldenFrameOfs <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ elsif (count = 2) then
+ LastFrameReconOfs <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ --elsif (count = 3) then
+ else
+ ThisFrameReconOfs <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= 0;
+ read_state <= stt_read_qtl;
+ end if;
+ end procedure ReadUniqFrameData;
+
+ procedure read_qtl is
+ begin
+ dqc_wr_e <= '0';
+
+ qtl_wr_e <= '1';
+ qtl_wr_data <= signed(in_data(15 downto 0));
+ qtl_wr_addr <= qtl_wr_addr + 1;
+
+ if (count = 0) then
+ qtl_wr_addr <= "000000";
+ count <= count + 1;
+ elsif (count = 63) then
+ count <= 0;
+ read_state <= stt_read2;
+ else
+ count <= count + 1;
+ end if;
+ end procedure read_qtl;
+
+ procedure read2 is
+ begin
+ qtl_wr_e <= '0';
+
+ if (count = 0) then
+ FragCodMeth_FragNumber <= unsigned(in_data(2 downto 0));
+ count <= count + 1;
+ elsif (count = 1) then
+-- FragCoefEOB_FragNumber <= unsigned(in_data(31 downto 0));
+ count <= count + 1;
+ elsif (count = 2) then
+ FragMVect_FragNumber_x <= in_data;
+ count <= count + 1;
+ elsif (count = 3) then
+ FragMVect_FragNumber_y <= in_data;
+ count <= count + 1;
+ elsif (count = 4) then
+ FragmentNumber <= unsigned(in_data);
+ pre_recon_state <= stt_PrepIDct;
+ read_state <= stt_read_qtl;
+ state <= stt_PreRecon;
+ s_in_request <= '0';
+ count <= 0;
+ end if;
+ end procedure read2;
+
+
+ procedure ReadIn is
+ begin
+ s_in_request <= '1';
+ if (s_in_request = '1' and in_valid = '1') then
+ case read_state is
+ when stt_read1 => read1;
+ when stt_read_uniq_frame_data => ReadUniqFrameData;
+ when stt_read_dqc => read_dqc;
+ when stt_read_qtl => read_qtl;
+ when others => read2;
+ end case;
+ end if;
+ end procedure ReadIn;
+
+
+-------------------------------------------------------------------------------
+-- Procedures called when state is stt_PreRecon
+-------------------------------------------------------------------------------
+
+ procedure PrepareToCallIDct is
+ begin
+ if (count = 0) then
+ -- Get coding mode for this block
+ if (FrameType = KEY_FRAME) then
+ CodingMode <= CODE_INTRA;
+ else
+ -- Get Motion vector and mode for this block.
+ CodingMode <= FragCodMeth_FragNumber;
+ end if;
+ count <= count + 1;
+ else
+ -- Select the appropriate inverse Q matrix and line stride
+ if (FragmentNumber < YPlaneFragments) then
+ ReconPixelsPerLine <= resize(YStride, MEM_ADDR_WIDTH);
+ MvShift <= "01";
+ MvModMask <= x"00000001";
+
+ -- Select appropriate dequantiser matrix.
+ if (CodingMode = CODE_INTRA) then
+ dequant_coeffs_Ofs <= Y_COEFFS_OFS;
+ else
+ dequant_coeffs_Ofs <= INTERY_COEFFS_OFS;
+ end if;
+ else
+ ReconPixelsPerLine <= resize(UVStride, MEM_ADDR_WIDTH);
+ MvShift <= "10";
+ MvModMask <= x"00000003";
+
+ -- Select appropriate dequantiser matrix.
+ if (CodingMode = CODE_INTRA) then
+ if (FragmentNumber < YPlaneFragments + UVPlaneFragments) then
+ dequant_coeffs_Ofs <= U_COEFFS_OFS;
+ else
+ dequant_coeffs_Ofs <= V_COEFFS_OFS;
+ end if;
+ else
+ if (FragmentNumber < YPlaneFragments + UVPlaneFragments) then
+ dequant_coeffs_Ofs <= INTERU_COEFFS_OFS;
+ else
+ dequant_coeffs_Ofs <= INTERV_COEFFS_OFS;
+ end if;
+ end if;
+ end if;
+ count <= 0;
+ pre_recon_state <= stt_CallIDct;
+ end if;
+ end procedure PrepareToCallIDct;
+
+ procedure CallIDct is
+ begin
+ if (out_idct_requested = '1') then
+ if (count = 0) then
+ qtl_rd_addr <= "000000";
+ dqc_rd_addr <= dequant_coeffs_Ofs;
+ count <= count + 1;
+ elsif (count = 1) then
+ -- Wait for the memory delay
+ qtl_rd_addr <= qtl_rd_addr + 1;
+ dqc_rd_addr <= dqc_rd_addr + 1;
+ count <= count + 1;
+ elsif (count = 64) then
+ out_idct_data <= dqc_rd_data;
+ out_idct_quantmat <= qtl_rd_data;
+ s_out_idct_valid <= '1';
+ count <= count + 1;
+ elsif (count = 65) then
+ out_idct_data <= dqc_rd_data;
+ out_idct_quantmat <= qtl_rd_data;
+ s_out_idct_valid <= '1';
+ -- IDct can process. The module will be waiting it
+ count <= 0;
+ pre_recon_state <= stt_RecIDct;
+ else
+ qtl_rd_addr <= qtl_rd_addr + 1;
+ dqc_rd_addr <= dqc_rd_addr + 1;
+
+ out_idct_data <= dqc_rd_data;
+ out_idct_quantmat <= qtl_rd_data;
+ s_out_idct_valid <= '1';
+ count <= count + 1;
+ end if;
+ end if;
+ end procedure CallIDct;
+
+ procedure RecIDct is
+ begin
+ s_out_idct_valid <= '0';
+ s_in_idct_request <= '1';
+ if (count = 64) then
+ pre_recon_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ count <= 0;
+ s_in_idct_request <= '0';
+ -- Convert fragment number to a pixel offset in a reconstruction buffer.
+ rpi_position <= resize(FragmentNumber, RPI_POS_WIDTH);
+ else
+ if (s_in_idct_request = '1' and in_idct_valid = '1') then
+ rdb_wr_e <= '1';
+ rdb_wr_addr <= rdb_wr_addr + 1;
+ rdb_wr_data <= in_idct_data;
+ if (count = 0) then
+ rdb_wr_addr <= "000000";
+ end if;
+ count <= count + 1;
+ end if;
+ end if;
+ end procedure RecIDct;
+
+
+ procedure CalcRPIValue is
+ begin
+ case calc_rpi_state is
+ when stt_calc_rpi1 =>
+ -- Wait until ReconPixelIndex can receive the data
+ if (s_rpi_out_requested = '1') then
+ calc_rpi_state <= stt_calc_rpi2;
+ end if;
+
+
+ when others =>
+ -- Wait until ReconPixelIndex returns the value
+ s_rpi_in_request <= '1';
+ if (s_rpi_in_request = '1' and s_rpi_in_valid = '1') then
+ rpi_value <= s_rpi_in_data;
+ s_rpi_in_request <= '0';
+ pre_recon_state <= stt_SelectRecons;
+ select_recons_state <= stt_SelectRecons_1;
+ end if;
+ end case;
+ end procedure CalcRPIValue;
+
+
+
+ procedure SelectRecons is
+ begin
+ if (select_recons_state = stt_SelectRecons_1) then
+ rdb_wr_e <= '0';
+ -- Action depends on decode mode.
+ if (CodingMode = CODE_INTER_NO_MV) then
+ -- Inter with no motion vector
+
+ -- Reconstruct the pixel data using the last frame Reconstructq'ction
+ -- and change data when the motion vector is (0,0), the recon is
+ -- based on the lastframe without loop filtering---- for testing
+ offset_ReconPtr <= resize(ThisFrameReconOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr <= resize(LastFrameReconOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr2 <= x"00000";
+ rdb_rd_addr <= "000000";
+ gotostate <= stt_Calculate_ReconInter;
+ recon_state <= stt_ReadPixels;
+ state <= stt_Recon;
+
+ elsif (ModeUsesMC(to_integer(CodingMode)) = '1') then
+ -- Work out the base motion vector offset and the 1/2 pixel offset
+ -- if any. For the U and V planes the MV specifies 1/4 pixel
+ -- accuracy. This is adjusted to 1/2 pixel as follows ( 0->0,
+ -- 1/4->1/2, 1/2->1/2, 3/4->1/2 ).
+
+ ReconPtr2Offset <= x"00000000";
+ MVOffset <= x"00000000";
+ if (FragMVect_FragNumber_x > ZERO_M_VECTOR) then
+ MVOffset <= SHIFT_RIGHT(FragMVect_FragNumber_x, to_integer(MvShift));
+ if ((FragMVect_FragNumber_x and signed(MvModMask)) /= x"00000000") then
+ ReconPtr2Offset <= x"00000001";
+ end if;
+ elsif (FragMVect_FragNumber_x < x"000000000") then
+ MVOffset <= - SHIFT_RIGHT(- FragMVect_FragNumber_x, to_integer(MvShift));
+ if (((-FragMVect_FragNumber_x) and signed(MvModMask)) /= x"00000000") then
+ ReconPtr2Offset <= x"FFFFFFFF";
+ end if;
+ end if;
+ select_recons_state <= stt_SelectRecons_2;
+
+ elsif (CodingMode = CODE_USING_GOLDEN) then
+ -- Golden frame with motion vector
+ -- Reconstruct the pixel data using the golden frame
+ -- reconstruction and change data
+ offset_ReconPtr <= resize(ThisFrameReconOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr <= resize(GoldenFrameOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr2 <= x"00000";
+ rdb_rd_addr <= "000000";
+ gotostate <= stt_Calculate_ReconInter;
+ recon_state <= stt_ReadPixels;
+ state <= stt_Recon;
+
+ else
+ -- Simple Intra coding
+ -- Get the pixel index for the first pixel in the fragment.
+ offset_ReconPtr <= resize(ThisFrameReconOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr <= x"00000";
+ offset_RefPtr2 <= x"00000";
+ rdb_rd_addr <= "000000";
+ gotostate <= stt_Calculate_ReconIntra;
+ recon_state <= stt_Calculate_ReconIntra;
+ state <= stt_Recon;
+ end if;
+
+
+ elsif (select_recons_state = stt_SelectRecons_2) then
+ if (FragMVect_FragNumber_y > ZERO_M_VECTOR) then
+ MVOffset <= resize(
+ MVOffset +
+ SHIFT_RIGHT(FragMVect_FragNumber_y, to_integer(MvShift)) *
+ signed('0' & ReconPixelsPerLine), 32);
+ if ((FragMVect_FragNumber_y and signed(MvModMask)) /= x"00000000") then
+ ReconPtr2Offset <= ReconPtr2Offset + signed('0' & ReconPixelsPerLine);
+ end if;
+ elsif (FragMVect_FragNumber_y < ZERO_M_VECTOR) then
+ MVOffset <= resize(
+ MVOffset -
+ SHIFT_RIGHT(-FragMVect_FragNumber_y, to_integer(MvShift)) *
+ signed('0' & ReconPixelsPerLine), 32);
+ if (((-FragMVect_FragNumber_y) and signed(MvModMask)) /= x"00000000") then
+ ReconPtr2Offset <= ReconPtr2Offset - signed('0' & ReconPixelsPerLine);
+ end if;
+ end if;
+ select_recons_state <= stt_SelectRecons_3;
+
+ elsif (select_recons_state = stt_SelectRecons_3) then
+ -- Set up the first of the two reconstruction buffer pointers.
+ if (CodingMode = CODE_GOLDEN_MV) then
+ LastFrameRecPtr <= resize(
+ unsigned(('0' & signed(GoldenFrameOfs)) +
+ rpi_value +
+ MVOffset), MEM_ADDR_WIDTH);
+ else
+ LastFrameRecPtr <= resize(
+ unsigned(('0' & signed(LastFrameReconOfs)) +
+ rpi_value +
+ MVOffset), MEM_ADDR_WIDTH);
+ end if;
+ select_recons_state <= stt_SelectRecons_4;
+
+ elsif (select_recons_state = stt_SelectRecons_4) then
+ -- Select the appropriate reconstruction function
+ if (ReconPtr2Offset = x"00000000") then
+ -- Reconstruct the pixel dats from the reference frame and change data
+ -- (no half pixel in this case as the two references were the same.
+ offset_ReconPtr <= resize(ThisFrameReconOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr <= LastFrameRecPtr;
+ offset_RefPtr2 <= x"00000";
+ rdb_rd_addr <= "000000";
+ gotostate <= stt_Calculate_ReconInter;
+ recon_state <= stt_ReadPixels;
+ state <= stt_Recon;
+ else
+ -- Fractional pixel reconstruction.
+ -- Note that we only use two pixels per reconstruction even for
+ -- the diagonal.
+ offset_ReconPtr <= resize(ThisFrameReconOfs +
+ unsigned(rpi_value), MEM_ADDR_WIDTH);
+ offset_RefPtr <= LastFrameRecPtr;
+ offset_RefPtr2 <= resize(
+ unsigned(signed('0' & LastFrameRecPtr) +
+ ReconPtr2Offset), MEM_ADDR_WIDTH);
+ rdb_rd_addr <= "000000";
+ gotostate <= stt_Calculate_ReconInterHalf;
+ recon_state <= stt_ReadPixels;
+ state <= stt_Recon;
+ end if;
+ end if;
+ end procedure SelectRecons;
+
+
+
+ procedure PreRecon is
+ begin
+ case pre_recon_state is
+ when stt_PrepIDct => PrepareToCallIDct;
+ when stt_CallIDct => CallIDct;
+ when stt_RecIDct => RecIDct;
+ when stt_Calc_RPI_Value => CalcRPIValue;
+ -- when stt_SelectRecons = other
+ when others => SelectRecons;
+ end case;
+ end procedure PreRecon;
+
+
+-------------------------------------------------------------------------------
+-- Procedures called when state is stt_Recon
+-------------------------------------------------------------------------------
+
+ ---------------------------------------------------------------------------
+ -- ReconIntra
+ ---------------------------------------------------------------------------
+ -- Parameters:
+ -- ReconPixelsPerLine - 'Distance' to the next buffer's pixel
+ -- gotostate - Must be stt_Calculate_ReconIntra
+ -- rdb_rd_addr - Must be zero
+ -- offset_ReconPtr - offset to write
+ -- offset_RefPtr - Must be zero
+ -- offset_RefPtr2 - Must be zero
+ procedure Calculate_ReconIntra is
+ begin
+ if (count = 8) then
+ out_done <= '1';
+ recon_calc_state <= stt_CalcRecon1;
+ state <= stt_EndProc;
+ count <= 0;
+ else
+ if (recon_calc_state = stt_CalcRecon1) then
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ recon_calc_state <= stt_CalcRecon2;
+
+ elsif (recon_calc_state = stt_CalcRecon2) then
+ sum <= rdb_rd_data + dC128;
+ recon_calc_state <= stt_CalcRecon3;
+ -- Wait the clamp
+
+ else
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ Pixel(colcount) <= sat;
+ colcount <= colcount + 1;
+ recon_calc_state <= stt_CalcRecon2;
+ if (colcount = 7) then
+ rdb_rd_addr <= rdb_rd_addr;
+ recon_state <= stt_WriteOut_Recon;
+ colcount <= 0;
+ recon_calc_state <= stt_CalcRecon1;
+ end if;
+ end if;
+ end if;
+ end procedure Calculate_ReconIntra;
+
+
+ procedure ReadPixels is
+ variable pointer : unsigned(1 downto 0);
+ begin
+ if (read_pixel_state = stt_ReadPixels1) then
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= stt_ReadPixels;
+ if (offset_RefPtr(1 downto 0) = "00") then
+ read_pixel_state <= stt_ReadPixels2;
+ else
+ read_pixel_state <= stt_ReadPixels4;
+ end if;
+
+ elsif (read_pixel_state = stt_ReadPixels2) then
+ Pixel(0) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel(1) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel(2) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel(3) <= unsigned(mem_rd_data(7 downto 0));
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr + 4, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= stt_ReadPixels;
+ read_pixel_state <= stt_ReadPixels3;
+
+ elsif (read_pixel_state = stt_ReadPixels3) then
+ Pixel(4) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel(5) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel(6) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel(7) <= unsigned(mem_rd_data(7 downto 0));
+ if (gotostate = stt_Calculate_ReconInter) then
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ end if;
+ -- The eigth pixels have already been brought from buffer
+ recon_state <= gotostate;
+ read_pixel_state <= stt_ReadPixels1;
+
+
+ elsif (read_pixel_state = stt_ReadPixels4) then
+ -- If offset_RefPtr is not a multiple of 4
+ case offset_RefPtr(1 downto 0) is
+ when "01" =>
+ Pixel(0) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel(1) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel(2) <= unsigned(mem_rd_data(7 downto 0));
+ when "10" =>
+ Pixel(0) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel(1) <= unsigned(mem_rd_data(7 downto 0));
+ when others =>
+ Pixel(0) <= unsigned(mem_rd_data(7 downto 0));
+ end case;
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr + 4, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= stt_ReadPixels;
+ read_pixel_state <= stt_ReadPixels5;
+
+ elsif (read_pixel_state = stt_ReadPixels5) then
+ case offset_RefPtr(1 downto 0) is
+ when "01" =>
+ pointer := "11";
+ when "10" =>
+ pointer := "10";
+ when others =>
+ pointer := "01";
+ end case;
+ Pixel(0 + to_integer(pointer)) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel(1 + to_integer(pointer)) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel(2 + to_integer(pointer)) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel(3 + to_integer(pointer)) <= unsigned(mem_rd_data(7 downto 0));
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr + 8, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= stt_ReadPixels;
+ read_pixel_state <= stt_ReadPixels6;
+
+ elsif (read_pixel_state = stt_ReadPixels6) then
+ case offset_RefPtr(1 downto 0) is
+ when "01" =>
+ Pixel(7) <= unsigned(mem_rd_data(31 downto 24));
+ when "10" =>
+ Pixel(6) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel(7) <= unsigned(mem_rd_data(23 downto 16));
+ when others =>
+ Pixel(5) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel(6) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel(7) <= unsigned(mem_rd_data(15 downto 8));
+ end case;
+ if (gotostate = stt_Calculate_ReconInter) then
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ end if;
+
+ -- The eigth pixels have already been brought from buffer
+ recon_state <= gotostate;
+ read_pixel_state <= stt_ReadPixels1;
+ end if;
+ end procedure ReadPixels;
+
+
+ ---------------------------------------------------------------------------
+ -- ReconInter
+ ---------------------------------------------------------------------------
+ -- Parameters:
+ -- ReconPixelsPerLine - 'Distance' to the next buffer's pixel
+ -- gotostate - Must be stt_ReadRefPtr
+ -- rdb_rd_addr - Must be zero
+ -- offset_ReconPtr - offset to write
+ -- offset_RefPtr - offset of the reference buffer
+ -- offset_RefPtr2 - Must be zero
+ procedure Calculate_ReconInter is
+ begin
+ if (count = 8) then
+ out_done <= '1';
+ recon_calc_state <= stt_CalcRecon1;
+ state <= stt_EndProc;
+ count <= 0;
+ else
+ if (recon_calc_state = stt_CalcRecon1) then
+ sum <= rdb_rd_data + ("000000000" & signed(Pixel(colcount)));
+ recon_calc_state <= stt_CalcRecon2;
+ -- Wait the clamp
+ else
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ Pixel(colcount) <= sat;
+ colcount <= colcount + 1;
+ recon_calc_state <= stt_CalcRecon1;
+ if (colcount = 7) then
+ rdb_rd_addr <= rdb_rd_addr;
+ recon_state <= stt_WriteOut_Recon;
+ colcount <= 0;
+ recon_calc_state <= stt_CalcRecon1;
+ end if;
+ end if;
+ end if;
+ end procedure Calculate_ReconInter;
+
+ ---------------------------------------------------------------------------
+ -- ReconInterHalf
+ ---------------------------------------------------------------------------
+ -- Parameters:
+ -- ReconPixelsPerLine - 'Distance' to the next buffer's pixel
+ -- gotostate - Must be stt_ReadRefPtr
+ -- rdb_rd_addr - Must be zero
+ -- offset_ReconPtr - offset to write
+ -- offset_RefPtr - offset of the first reference buffer
+ -- offset_RefPtr2 - offset of the second reference buffer
+
+ procedure Calculate_ReconInterHalf is
+ variable pointer : unsigned(1 downto 0);
+ begin
+ if (count = 8) then
+ out_done <= '1';
+ recon_calc_state <= stt_CalcRecon1;
+ state <= stt_EndProc;
+ count <= 0;
+ else
+ if (recon_calc_state = stt_CalcRecon1) then
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr2, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= gotostate;
+ -- if offset_RefPtr2 mod 4 = 0
+ if (offset_RefPtr2(1 downto 0) = "00") then
+ recon_calc_state <= stt_CalcRecon2;
+ else
+ recon_calc_state <= stt_CalcRecon4;
+ end if;
+
+ elsif (recon_calc_state = stt_CalcRecon2) then
+ Pixel1(0) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel1(1) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel1(2) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel1(3) <= unsigned(mem_rd_data(7 downto 0));
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr2 + 4, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= gotostate;
+ recon_calc_state <= stt_CalcRecon3;
+
+ elsif (recon_calc_state = stt_CalcRecon3) then
+ Pixel1(4) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel1(5) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel1(6) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel1(7) <= unsigned(mem_rd_data(7 downto 0));
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ recon_calc_state <= stt_CalcRecon7;
+
+
+ elsif (recon_calc_state = stt_CalcRecon4) then
+ -- If offset_RefPtr2 is not a multiple of 4
+ case offset_RefPtr2(1 downto 0) is
+ when "01" =>
+ Pixel1(0) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel1(1) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel1(2) <= unsigned(mem_rd_data(7 downto 0));
+ when "10" =>
+ Pixel1(0) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel1(1) <= unsigned(mem_rd_data(7 downto 0));
+ when others =>
+ Pixel1(0) <= unsigned(mem_rd_data(7 downto 0));
+ end case;
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr2 + 4, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= gotostate;
+ recon_calc_state <= stt_CalcRecon5;
+
+ elsif (recon_calc_state = stt_CalcRecon5) then
+ case offset_RefPtr2(1 downto 0) is
+ when "01" =>
+ pointer := "11";
+ when "10" =>
+ pointer := "10";
+ when others =>
+ pointer := "01";
+ end case;
+ Pixel1(0 + to_integer(pointer)) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel1(1 + to_integer(pointer)) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel1(2 + to_integer(pointer)) <= unsigned(mem_rd_data(15 downto 8));
+ Pixel1(3 + to_integer(pointer)) <= unsigned(mem_rd_data(7 downto 0));
+ s_in_sem_request <= '1';
+ in_sem_addr <= SHIFT_RIGHT(offset_RefPtr2 + 8, 2);
+ recon_state <= stt_ReadMemory;
+ gotostate2 <= gotostate;
+ recon_calc_state <= stt_CalcRecon6;
+
+ elsif (recon_calc_state = stt_CalcRecon6) then
+ case offset_RefPtr2(1 downto 0) is
+ when "01" =>
+ Pixel1(7) <= unsigned(mem_rd_data(31 downto 24));
+ when "10" =>
+ Pixel1(6) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel1(7) <= unsigned(mem_rd_data(23 downto 16));
+ when others =>
+ Pixel1(5) <= unsigned(mem_rd_data(31 downto 24));
+ Pixel1(6) <= unsigned(mem_rd_data(23 downto 16));
+ Pixel1(7) <= unsigned(mem_rd_data(15 downto 8));
+ end case;
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ recon_calc_state <= stt_CalcRecon7;
+
+ elsif (recon_calc_state = stt_CalcRecon7) then
+ sum <= rdb_rd_data +
+ SHIFT_RIGHT(
+ ("000000000" & signed(Pixel(colcount))) +
+ ("000000000" & signed(Pixel1(colcount))) , 1);
+ recon_calc_state <= stt_CalcRecon8;
+ -- Wait the clamp
+
+ else
+ rdb_rd_addr <= rdb_rd_addr + 1;
+ Pixel(colcount) <= sat;
+ colcount <= colcount + 1;
+ recon_calc_state <= stt_CalcRecon7;
+ if (colcount = 7) then
+ rdb_rd_addr <= rdb_rd_addr;
+ recon_state <= stt_WriteOut_Recon;
+ colcount <= 0;
+ recon_calc_state <= stt_CalcRecon1;
+ end if;
+ end if;
+ end if;
+ end procedure Calculate_ReconInterHalf;
+
+
+ procedure WriteOut_Recon is
+ begin
+
+ if (write_recon_state = stt_WriteRecon1) then
+ out_sem_addr <= SHIFT_RIGHT(offset_ReconPtr, 2);
+ out_sem_data <= signed(Pixel(0)) &
+ signed(Pixel(1)) &
+ signed(Pixel(2)) &
+ signed(Pixel(3));
+ s_out_sem_valid <= '1';
+ write_recon_state <= stt_WriteRecon2;
+ recon_state <= stt_WriteMemory;
+
+ elsif (write_recon_state <= stt_WriteRecon2) then
+ out_sem_addr <= SHIFT_RIGHT(offset_ReconPtr + 4, 2);
+ out_sem_data <= signed(Pixel(4)) &
+ signed(Pixel(5)) &
+ signed(Pixel(6)) &
+ signed(Pixel(7));
+ s_out_sem_valid <= '1';
+ write_recon_state <= stt_WriteReconLast;
+ recon_state <= stt_WriteMemory;
+
+ else
+ --write_recon_state = stt_WriteReconLast;
+ write_recon_state <= stt_WriteRecon1;
+
+ recon_state <= stt_ReadPixels;
+ if (gotostate = stt_Calculate_ReconIntra) then
+ recon_state <= gotostate;
+ end if;
+
+ offset_ReconPtr <= offset_ReconPtr + ReconPixelsPerLine;
+ offset_RefPtr <= offset_RefPtr + ReconPixelsPerLine;
+ offset_RefPtr2 <= offset_RefPtr2 + ReconPixelsPerLine;
+ count <= count + 1;
+ end if;
+ end procedure WriteOut_Recon;
+
+ procedure ReadMemory is
+ begin
+ s_in_sem_request <= '1';
+ if (s_in_sem_request = '1' and in_sem_valid = '1') then
+ mem_rd_data <= in_sem_data;
+ s_in_sem_request <= '0';
+ recon_state <= gotostate2;
+ end if;
+ end procedure ReadMemory;
+
+
+
+ procedure WriteMemory is
+ begin
+ if (out_sem_requested = '1') then
+ recon_state <= stt_WriteOut_Recon;
+ s_out_sem_valid <= '0';
+ end if;
+ end procedure WriteMemory;
+
+ procedure Recon is
+ begin
+ case recon_state is
+ when stt_WriteOut_Recon => WriteOut_Recon;
+ when stt_WriteMemory => WriteMemory;
+ when stt_ReadMemory => ReadMemory;
+ when stt_ReadPixels => ReadPixels;
+ when stt_Calculate_ReconInterHalf => Calculate_ReconInterHalf;
+ when stt_Calculate_ReconInter => Calculate_ReconInter;
+ --when stt_Calculate_ReconIntra => Calculate_ReconIntra;
+ when others => Calculate_ReconIntra;
+ end case;
+ end procedure Recon;
+
+
+-------------------------------------------------------------------------------
+-- Procedures called when state is stt_EndProc
+-------------------------------------------------------------------------------
+ procedure EndProc is
+ begin
+ count <= 0;
+ out_done <= '0';
+ state <= stt_readIn;
+ end procedure EndProc;
+
+ begin -- process
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ state <= stt_readIn;
+ read_state <= stt_read1;
+ pre_recon_state <= stt_PrepIDct;
+ select_recons_state <= stt_SelectRecons_1;
+ read_pixel_state <= stt_ReadPixels1;
+ write_recon_state <= stt_WriteRecon1;
+
+ s_in_request <= '0';
+ s_in_sem_request <= '0';
+ count <= 0;
+ s_out_sem_valid <= '0';
+ out_done <= '0';
+
+ s_out_idct_valid <= '0';
+ s_in_idct_request <= '0';
+
+
+ colcount <= 0;
+ sum <= '0' & x"0000";
+
+ rpi_position <= '0' & x"0000";
+-- HFragments <= x"11";
+-- VFragments <= x"00";
+ YStride <= x"000";
+ UVStride <= "000" & x"00";
+ YPlaneFragments <= '0' & x"00000";
+ UVPlaneFragments <= "000" & x"0000";
+-- ReconYDataOffset <= x"00000";
+-- ReconUDataOffset <= x"00000";
+-- ReconVDataOffset <= x"00000";
+
+ qtl_wr_e <= '0';
+ qtl_wr_addr <= "000000";
+ qtl_wr_data <= "0000000000000000";
+ qtl_rd_addr <= "000000";
+
+ dqc_wr_e <= '0';
+ dqc_wr_addr <= "000000000";
+ dqc_wr_data <= "0000000000000000";
+ dqc_rd_addr <= "000000000";
+
+ rdb_wr_e <= '0';
+ rdb_wr_addr <= "000000";
+ rdb_wr_data <= "0000000000000000";
+ rdb_rd_addr <= "000000";
+
+
+ else
+ s_in_request <= '0';
+ if (Enable = '1') then
+ -- If is a new frame should read the dequantized matrix again.
+ if (in_newframe = '1') then
+ read_state <= stt_read_dqc;
+ end if;
+
+ case state is
+ when stt_readIn => ReadIn;
+ when stt_PreRecon => PreRecon;
+ when stt_Recon => Recon;
+ when others => EndProc;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+end a_ExpandBlock;
Property changes on: trunk/theora-fpga/theora_hardware/expandblock.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/idctslow.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/idctslow.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/idctslow.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,349 @@
+-------------------------------------------------------------------------------
+-- Description: Do the iDCTSlow job.
+-------------------------------------------------------------------------------
+
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+
+entity IDctSlow is
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(15 downto 0);
+ in_quantmat : in signed(15 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(15 downto 0)
+ );
+end entity IDctSlow;
+
+
+architecture rtl of IDctSlow is
+ component dual_syncram
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd1_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd1_data : out signed(DATA_WIDTH-1 downto 0);
+ rd2_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd2_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+ end component;
+
+
+ subtype ogg_int_16_t is signed(15 downto 0);
+ subtype ogg_int_32_t is signed(31 downto 0);
+
+ type mem64_t is array (0 to 63) of ogg_int_16_t;
+
+ signal s_A, s_B, s_C, s_D, s_Ad, s_Bd, s_Cd, s_Dd, s_E, s_F, s_G, s_H : ogg_int_16_t;
+ signal s_Ed, s_Gd, s_Add, s_Bdd, s_Fd, s_Hd : ogg_int_16_t;
+
+ signal row_loop : std_logic;
+
+-- FSMs
+ type state_t is (readIn,idct,writeOut);
+ signal state : state_t;
+
+ type idct_state_t is (idct_st1, idct_st2, idct_st3, idct_st4,
+ idct_st5, idct_st6, idct_st7, idct_st8,
+ idct_st9, idct_st10, idct_st11, idct_st12,
+ idct_st13, idct_st14, idct_st15, idct_st16);
+ signal idct_state : idct_state_t;
+
+ type wout_state_t is (wout_st1, wout_st2, wout_st3);
+ signal wout_state : wout_state_t;
+
+-- Memory
+
+ signal mem_we : std_logic;
+ signal mem_waddr : unsigned(5 downto 0);
+ signal mem_wdata : ogg_int_16_t;
+ signal mem_raddr1 : unsigned(5 downto 0);
+ signal mem_rdata1 : ogg_int_16_t;
+ signal mem_raddr2 : unsigned(5 downto 0);
+ signal mem_rdata2 : ogg_int_16_t;
+
+-- Handshake
+ subtype tiny_int is integer range 0 to 63;
+ signal count : tiny_int;
+ signal s_in_request : std_logic;
+ signal s_out_valid : std_logic;
+
+
+ type dezigzag_t is array (0 to 63) of unsigned(5 downto 0);
+ constant dezigzag_index : dezigzag_t := (
+ "000000", "000001", "001000", "010000", "001001",
+ "000010", "000011", "001010", "010001", "011000",
+ "100000", "011001", "010010", "001011", "000100",
+ "000101", "001100", "010011", "011010", "100001",
+ "101000", "110000", "101001", "100010", "011011",
+ "010100", "001101", "000110", "000111", "001110",
+ "010101", "011100", "100011", "101010", "110001",
+ "111000", "111001", "110010", "101011", "100100",
+ "011101", "010110", "001111", "010111", "011110",
+ "100101", "101100", "110011", "111010", "111011",
+ "110100", "101101", "100110", "011111", "100111",
+ "101110", "110101", "111100", "111101", "110110",
+ "101111", "110111", "111110", "111111" );
+
+
+
+-- cos(n*pi/16) or sin(8-n)*pi/16)
+ constant xC1S7 : ogg_int_32_t := "00000000000000001111101100010101";
+ constant xC2S6 : ogg_int_32_t := "00000000000000001110110010000011";
+ constant xC3S5 : ogg_int_32_t := "00000000000000001101010011011011";
+ constant xC4S4 : ogg_int_32_t := "00000000000000001011010100000101";
+ constant xC5S3 : ogg_int_32_t := "00000000000000001000111000111010";
+ constant xC6S2 : ogg_int_32_t := "00000000000000000110000111111000";
+ constant xC7S1 : ogg_int_32_t := "00000000000000000011000111110001";
+
+
+begin
+
+ -- Data matrix 8 x 8 x 16 bits
+ mem : dual_syncram
+ generic map( DEPTH => 64, DATA_WIDTH => 16, ADDR_WIDTH => 6 )
+ port map(clk, mem_we, mem_waddr, mem_wdata, mem_raddr1, mem_rdata1, mem_raddr2, mem_rdata2 );
+
+ in_request <= s_in_request;
+ out_valid <= s_out_valid;
+ out_data <= mem_rdata1;
+
+
+ process(clk)
+
+ procedure ReadIn is
+ begin
+ s_out_valid <= '0'; -- came from WriteOut, out_valid must be 0
+ s_in_request <= '1';
+
+ if( s_in_request = '1' and in_valid = '1' )then
+ mem_waddr <= dezigzag_index( count );
+ mem_wdata <= "*"( in_data, in_quantmat )(15 downto 0);
+ mem_we <= '1';
+
+ if( count = 63 )then
+ state <= idct;
+ s_in_request <= '0';
+ count <= 0;
+ else
+ count <= count + 1;
+ end if;
+
+ end if;
+ end procedure ReadIn;
+
+
+ procedure WriteOut is
+ begin
+ case wout_state is
+ when wout_st1 =>
+ wout_state <= wout_st2;
+ mem_raddr1 <= to_unsigned(count,6);
+
+ when wout_st2 => -- Wait for the memory delay
+ wout_state <= wout_st3;
+ s_out_valid <= '0';
+
+ when wout_st3 =>
+ s_out_valid <= '1';
+
+ if( out_requested = '1' )then
+ if( count = 63 )then
+ wout_state <= wout_st1;
+ state <= readIn; -- on readIn state must set out_valid to 0
+ count <= 0;
+ else
+ wout_state <= wout_st2;
+ mem_raddr1 <= to_unsigned(count + 1,6);
+ count <= count + 1;
+ end if;
+ end if;
+
+ when others => null;
+ end case;
+ end procedure WriteOut;
+
+
+
+ procedure Idct is
+ variable adjust: integer range 0 to 8;
+ variable adjidx : integer range 0 to 8;
+ variable shift : integer range 0 to 4;
+ begin
+ if (row_loop = '1') then
+ adjust := 0;
+ shift := 0;
+ adjidx := 1;
+ else
+ adjust := 8;
+ shift := 4;
+ adjidx := 8;
+ end if;
+
+ case idct_state is
+ when idct_st1 =>
+ idct_state <= idct_st2;
+ mem_raddr1 <= to_unsigned(1*adjidx + count,6);
+ mem_raddr2 <= to_unsigned(7*adjidx + count,6);
+ when idct_st2 =>
+ idct_state <= idct_st3;
+ mem_raddr1 <= to_unsigned(3*adjidx + count,6);
+ mem_raddr2 <= to_unsigned(5*adjidx + count,6);
+ when idct_st3 =>
+ idct_state <= idct_st4;
+ s_A <= "*"(xC1S7,mem_rdata1)(31 downto 16) + "*"(xC7S1,mem_rdata2)(31 downto 16);
+ s_B <= "*"(xC7S1,mem_rdata1)(31 downto 16) - "*"(xC1S7,mem_rdata2)(31 downto 16);
+ mem_raddr1 <= to_unsigned(3*adjidx + count,6);
+ mem_raddr2 <= to_unsigned(5*adjidx + count,6);
+
+ when idct_st4 =>
+ idct_state <= idct_st5;
+ s_C <= "*"(xC3S5,mem_rdata1)(31 downto 16) + "*"(xC5S3,mem_rdata2)(31 downto 16);
+ s_D <= "*"(xC3S5,mem_rdata2)(31 downto 16) - "*"(xC5S3,mem_rdata1)(31 downto 16);
+ mem_raddr1 <= to_unsigned(0*adjidx + count,6);
+ mem_raddr2 <= to_unsigned(4*adjidx + count,6);
+ when idct_st5 =>
+ idct_state <= idct_st6;
+ s_Ad <= "*"(xC4S4,(s_A - s_C))(31 downto 16);
+ s_Bd <= "*"(xC4S4,(s_B - s_D))(31 downto 16);
+ s_Cd <= s_A + s_C;
+ s_Dd <= s_B + s_D;
+ mem_raddr1 <= to_unsigned(2*adjidx + count,6);
+ mem_raddr2 <= to_unsigned(6*adjidx + count,6);
+
+ when idct_st6 =>
+ idct_state <= idct_st7;
+ s_E <= "*"(xC4S4,(mem_rdata1 + mem_rdata2))(31 downto 16);
+ s_F <= "*"(xC4S4,(mem_rdata1 - mem_rdata2))(31 downto 16);
+
+ when idct_st7 =>
+ idct_state <= idct_st8;
+ s_G <= "*"(xC2S6,mem_rdata1)(31 downto 16) + "*"(xC6S2,mem_rdata2)(31 downto 16);
+ s_H <= "*"(xC6S2,mem_rdata1)(31 downto 16) - "*"(xC2S6,mem_rdata2)(31 downto 16);
+
+ when idct_st8 =>
+ idct_state <= idct_st9;
+ s_Ed <= s_E - s_G + adjust;
+ s_Gd <= s_E + s_G + adjust;
+ s_Add <= s_F + s_Ad + adjust;
+ s_Fd <= s_F - s_Ad + adjust;
+ s_Bdd <= s_Bd - s_H;
+ s_Hd <= s_Bd + s_H;
+
+ when idct_st9 =>
+ idct_state <= idct_st10;
+ mem_waddr <= to_unsigned(0*adjidx + count,6);
+ mem_wdata <= shift_right(s_Gd + s_Cd,shift);
+ mem_we <= '1';
+
+ when idct_st10 =>
+ idct_state <= idct_st11;
+ mem_waddr <= to_unsigned(7*adjidx + count,6);
+ mem_wdata <= shift_right(s_Gd - s_Cd,shift);
+ mem_we <= '1';
+
+ when idct_st11 =>
+ idct_state <= idct_st12;
+ mem_waddr <= to_unsigned(1*adjidx + count,6);
+ mem_wdata <= shift_right(s_Add + s_Hd,shift);
+ mem_we <= '1';
+
+ when idct_st12 =>
+ idct_state <= idct_st13;
+ mem_waddr <= to_unsigned(2*adjidx + count,6);
+ mem_wdata <= shift_right(s_Add - s_Hd,shift);
+ mem_we <= '1';
+
+ when idct_st13 =>
+ idct_state <= idct_st14;
+ mem_waddr <= to_unsigned(3*adjidx + count,6);
+ mem_wdata <= shift_right(s_Ed + s_Dd,shift);
+ mem_we <= '1';
+
+ when idct_st14 =>
+ idct_state <= idct_st15;
+ mem_waddr <= to_unsigned(4*adjidx + count,6);
+ mem_wdata <= shift_right(s_Ed - s_Dd,shift);
+ mem_we <= '1';
+
+ when idct_st15 =>
+ idct_state <= idct_st16;
+ mem_waddr <= to_unsigned(5*adjidx + count,6);
+ mem_wdata <= shift_right(s_Fd + s_Bdd,shift);
+ mem_we <= '1';
+
+ when idct_st16 =>
+ idct_state <= idct_st1;
+ mem_waddr <= to_unsigned(6*adjidx + count,6);
+ mem_wdata <= shift_right(s_Fd - s_Bdd,shift);
+ mem_we <= '1';
+
+ if (row_loop = '1') then
+ if ( count = 56 ) then
+ count <= 0;
+ row_loop <= '0';
+ else
+ count <= count + 8;
+ end if;
+ else
+ if ( count = 7 ) then
+ count <= 0;
+ row_loop <= '1';
+ state <= writeOut;
+ else
+ count <= count + 1;
+ end if;
+ end if;
+ when others => null;
+ end case;
+ end procedure Idct;
+
+
+ begin
+
+ if(clk'event and clk = '1') then
+ if( Reset_n = '0' ) then
+ state <= readIn;
+ idct_state <= idct_st1;
+ wout_state <= wout_st1;
+ s_in_request <= '0';
+ count <= 0;
+ s_out_valid <= '0';
+ row_loop <= '1';
+ mem_we <= '0';
+
+ mem_waddr <= "000000";
+ mem_wdata <= "0000000000000000";
+ mem_raddr1 <= "000000";
+ mem_raddr2 <= "000000";
+ else
+ mem_we <= '0';
+ case state is
+ when readIn => ReadIn;
+ when idct => Idct;
+ when writeOut => WriteOut;
+ when others => ReadIn; state <= readIn;
+ end case;
+ end if;
+ end if;
+ end process;
+
+end rtl;
Property changes on: trunk/theora-fpga/theora_hardware/idctslow.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/interface_vga.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/interface_vga.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/interface_vga.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,304 @@
+-------------------------------------------------------------------------------
+-- Title : Interface VGA
+-- Project : theora-fpga
+-------------------------------------------------------------------------------
+-- File : interface_vga.vhd
+-- Author : Leonardo de Paula Rosa Piga
+-- Company : LSC - IC - UNICAMP
+-- Last update: 2007/08/23
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description: Send the pixels from the RGB memory to the video controller
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity interface_vga is
+ generic (
+ DEPTH : natural := 8192; -- RGB MEMORY DEPTH
+ ADDR_WIDTH : natural := 13; -- RGB MEMORY ADDRESS WIDTH
+ DATA_WIDTH : natural := 24; -- RGB MEMORY DATA WIDTH
+ ZOOM : natural range 0 to 7 := 4 -- Image will be scaled to ZOOM
+ );
+
+ port(
+ video_clock : in std_logic;
+ reset_n : in std_logic; -- reset
+
+
+ ---------------------------------------------------------------------------
+ -- Ports of RGB frame memory
+ ---------------------------------------------------------------------------
+ rgb_rd_addr : out unsigned(ADDR_WIDTH-1 downto 0);
+ rgb_rd_data : in signed(DATA_WIDTH-1 downto 0);
+
+ ---------------------------------------------------------------------------
+ -- Port of RGB frame memory control access
+ ---------------------------------------------------------------------------
+ can_read_mem : in std_logic;
+
+ video_width : in unsigned(11 downto 0);
+ video_height : in unsigned(11 downto 0);
+
+ red : out std_logic_vector(7 downto 0); -- red component
+ green : out std_logic_vector(7 downto 0); -- green component
+ blue : out std_logic_vector(7 downto 0); -- blue component
+ line_pixel : out std_logic_vector(9 downto 0); -- compute line
+ column_pixel : out std_logic_vector(9 downto 0); -- compute column
+ m1, m2 : out std_logic; -- select dac mode
+ blank_n : out std_logic; -- dac command
+ sync_n : out std_logic; -- dac command
+ sync_t : out std_logic; -- dac command
+ video_clk : out std_logic; -- dac command
+ vga_vs : out std_logic; -- vertical sync
+ vga_hs : out std_logic -- horizontal sync
+ );
+end interface_vga;
+
+
+architecture a_lancelot of interface_vga is
+ constant HORIZ_RES : natural := 640; -- Horizontal Resolution
+ constant HSYNC_BACK_PORCH_W : natural := 40;
+ constant HSYNC_FRONT_PORCH_W : natural := 25;
+ constant HSYNC_PULSE_WIDTH : natural := 95;
+ constant VERT_RES : natural := 480; -- Vertical Resolution
+ constant VSYNC_BACK_PORCH_W : natural := 22;
+ constant VSYNC_FRONT_PORCH_W : natural := 10;
+ constant VSYNC_PULSE_W : natural := 2;
+
+
+
+-- constant HORIZ_RES : natural := 160; -- Horizontal Resolution
+-- constant HSYNC_BACK_PORCH_W : natural := 40;
+-- constant HSYNC_FRONT_PORCH_W : natural := 25;
+-- constant HSYNC_PULSE_WIDTH : natural := 95;
+-- constant VERT_RES : natural := 120; -- Vertical Resolution
+-- constant VSYNC_BACK_PORCH_W : natural := 22;
+-- constant VSYNC_FRONT_PORCH_W : natural := 10;
+-- constant VSYNC_PULSE_W : natural := 2;
+
+
+-- DAC State Machine
+ type dac_mode_state_type is
+ (
+ ds0, ds1, ds2, ds3, ds4
+ );
+ signal dac_mode_current_state, dac_mode_next_state : dac_mode_state_type;
+
+ type sync_mem_state_t is (stt_sync_mem1, stt_sync_mem2);
+ signal sync_mem_state : sync_mem_state_t;
+
+ signal count_h, count_v : natural RANGE 0 TO 2043;
+ signal video_on_v, video_on_h : std_logic;
+ signal s_rgb_rd_addr : unsigned(ADDR_WIDTH-1 downto 0);
+ signal repeat_line : natural range 0 to 7;
+ signal repeat_col : natural range 0 to 7;
+
+ signal count_disp_c : natural RANGE 0 TO 1023;
+
+begin
+ -- fixed signals
+ video_clk <= '1';--video_clock
+
+ blank_n <= video_on_h and video_on_v;
+
+ rgb_rd_addr <= s_rgb_rd_addr;
+----------------------------------
+-- Video DAC Mode state machine --
+----------------------------------
+-- Set DAC in RGB mode and bias on all three channels
+
+ process(video_clock, reset_n)
+ begin
+ if reset_n = '0' then
+ dac_mode_current_state <= ds0;
+ elsif (video_clock'event and video_clock = '1') then
+ dac_mode_current_state <= dac_mode_next_state after 5 ns;
+ end if;
+ end process;
+
+ process(dac_mode_current_state)
+ begin
+
+ sync_n <= '0';
+ m2 <= '0';
+ m1 <= '0';
+ sync_t <= '0';
+ case dac_mode_current_state is
+
+ when ds0 =>
+ dac_mode_next_state <= ds1;
+
+ when ds1 =>
+ sync_n <= '1';
+ m2 <= '0';
+ m1 <= '0';
+ sync_t <= '0';
+ dac_mode_next_state <= ds2;
+
+ -- bias on all three channels
+ when ds2 =>
+ sync_n <= '0';
+ m2 <= '1';
+ m1 <= '0';
+ sync_t <= '0';
+ dac_mode_next_state <= ds3;
+
+ when ds3 =>
+ sync_n <= '0';
+ m2 <= '1';
+ m1 <= '0';
+ sync_t <= '0';
+ dac_mode_next_state <= ds4;
+
+ -- RGB mode
+ when ds4 =>
+ sync_n <= '1';
+ m2 <= '0';
+ m1 <= '0';
+ sync_t <= '0';
+ dac_mode_next_state <= ds4;
+
+ when others =>
+ sync_n <= '1';
+ m2 <= '0';
+ m1 <= '0';
+ sync_t <= '0';
+ dac_mode_next_state <= ds0;
+
+ end case;
+
+ end process;
+
+ timing: process (video_clock, reset_n)
+ variable scale_x : natural range 0 to 16383;
+ variable scale_y : natural range 0 to 16383;
+ begin -- process timing
+ if reset_n = '0' then -- asynchronous reset (active low)
+ count_v <= 0;
+ count_h <= 0;
+ vga_hs <= '1';
+ vga_vs <= '1';
+ video_on_h <= '1';
+ video_on_v <= '1';
+
+ red <= x"00";
+ green <= x"00";
+ blue <= x"00";
+ sync_mem_state <= stt_sync_mem1;
+ s_rgb_rd_addr <= (others => '0');
+ line_pixel <= (others => '1');
+ column_pixel <= (others => '1');
+
+ repeat_line <= 0;
+ repeat_col <= 0;
+ count_disp_c <= 0;
+
+ elsif video_clock'event and video_clock = '1' then -- rising clock edge
+
+ if (sync_mem_state = stt_sync_mem2) then
+ if (count_h = (HORIZ_RES +
+ HSYNC_BACK_PORCH_W +
+ HSYNC_FRONT_PORCH_W +
+ HSYNC_PULSE_WIDTH) - 1
+ ) then
+ count_h <= 0;
+
+ if (count_v = (VERT_RES +
+ VSYNC_BACK_PORCH_W +
+ VSYNC_FRONT_PORCH_W +
+ VSYNC_PULSE_W) - 1
+ ) then
+ count_v <= 0;
+ else
+ count_v <= count_v + 1;
+ end if;
+
+ else
+ count_h <= count_h + 1;
+ end if;
+
+ if ((count_h >= HORIZ_RES + HSYNC_FRONT_PORCH_W) and
+ (count_h < HORIZ_RES + HSYNC_FRONT_PORCH_W + HSYNC_PULSE_WIDTH)) then
+ vga_hs <= '0';
+ else
+ vga_hs <= '1';
+ end if;
+
+ if ((count_v >= VERT_RES + VSYNC_FRONT_PORCH_W) and
+ (count_v < VERT_RES + VSYNC_FRONT_PORCH_W + VSYNC_PULSE_W)) then
+ vga_vs <= '0';
+ else
+ vga_vs <= '1';
+ end if;
+
+ -- blank_n signal
+ if count_h < HORIZ_RES then
+ video_on_h <= '1';
+ column_pixel <= std_logic_vector(to_unsigned(count_h,10));
+ else
+ video_on_h <= '0';
+ end if;
+
+ if count_v < VERT_RES then
+ video_on_v <= '1';
+ line_pixel <= std_logic_vector(to_unsigned(count_v, 10));
+ else
+ video_on_v <= '0';
+ end if;
+ end if;
+
+ if (can_read_mem = '1') then
+
+ case sync_mem_state is
+ when stt_sync_mem1 =>
+ s_rgb_rd_addr <= (others => '0');
+ sync_mem_state <= stt_sync_mem2;
+
+-- when stt_sync_mem2 =>
+-- s_rgb_rd_addr <= s_rgb_rd_addr + 1;
+-- sync_mem_state <= stt_sync_mem3;
+
+ when others =>
+ red <= x"00";
+ green <= x"00";
+ blue <= x"00";
+ scale_x := to_integer(video_width * ZOOM);
+ scale_y := to_integer(video_height * ZOOM);
+ if (count_h >=0 and count_h < scale_x) then
+ if (count_v >=0 and count_v < scale_y) then
+ red <= std_logic_vector(rgb_rd_data(23 downto 16));
+ green <= std_logic_vector(rgb_rd_data(15 downto 8));
+ blue <= std_logic_vector(rgb_rd_data(7 downto 0));
+
+
+ repeat_col <= repeat_col + 1;
+ if (repeat_col = ZOOM - 1) then
+ repeat_col <= 0;
+ s_rgb_rd_addr <= s_rgb_rd_addr + 1;
+ count_disp_c <= count_disp_c + 1;
+
+ if (count_disp_c = video_width - 1) then
+ s_rgb_rd_addr <= s_rgb_rd_addr - (video_width - 1);
+ count_disp_c <= 0;
+ repeat_line <= repeat_line + 1;
+ if (repeat_line = ZOOM - 1) then
+ repeat_line <= 0;
+
+ s_rgb_rd_addr <= s_rgb_rd_addr + 1;
+ if (s_rgb_rd_addr = video_width * video_height - 1) then
+ s_rgb_rd_addr <= (others => '0');
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end if;
+ end case;
+ end if;
+ end if;
+ end process timing;
+
+end a_lancelot;
Property changes on: trunk/theora-fpga/theora_hardware/interface_vga.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/lflimits.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/lflimits.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/lflimits.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,36 @@
+-------------------------------------------------------------------------------
+-- Description: This file implements a component that calculate
+-- the filtbounding on-the-fly.
+-------------------------------------------------------------------------------
+
+library std;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity LFLimits is
+
+ port (
+ parameter : in unsigned(8 downto 0);
+ FLimit : in signed(8 downto 0);
+
+ fbv_value : out signed(9 downto 0));
+
+end LFLimits;
+
+architecture a_LFLimits of LFLimits is
+
+begin -- a_LFLimits
+
+ fbv_value <=
+ "0000000000"
+ when ((parameter <= 256 - unsigned(2*('0' & FLimit))) or
+ (parameter >= 256 + unsigned(2*('0' & FLimit)))) else
+ ('0' & signed(parameter)) - "0100000000"
+ when ((parameter > 256 - unsigned(FLimit)) and
+ (parameter < 256 + unsigned(FLimit))) else
+ resize(256 - 2*('0' & FLimit) - ('0' & signed(parameter)), 10)
+ when ((parameter > 256 - unsigned(2*('0' & FLimit))) and
+ (parameter <= 256 - unsigned(FLimit))) else
+ resize(256 + 2*('0' & FLimit) -('0' & signed(parameter)), 10);
+end a_LFLimits;
Property changes on: trunk/theora-fpga/theora_hardware/lflimits.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/loopfilter.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/loopfilter.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/loopfilter.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,1904 @@
+-------------------------------------------------------------------------------
+-- Description: This file implements the loopfilter. A filter that do
+-- a deblocking on the fragments.
+-------------------------------------------------------------------------------
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+
+entity LoopFilter is
+
+ port (Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic
+ );
+end LoopFilter;
+
+architecture a_LoopFilter of LoopFilter is
+ component tsyncram
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+ end component;
+
+ component ReconPixelIndex
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+ end component;
+
+ component LFLimits
+ port (
+ parameter : in unsigned(8 downto 0);
+ FLimit : in signed(8 downto 0);
+ fbv_value : out signed(9 downto 0));
+ end component;
+
+
+ -- We are using 1024 as the maximum width and height size
+ -- = ceil(log2(Maximum Size))
+ constant LG_MAX_SIZE : natural := 10;
+ constant MEM_ADDR_WIDTH : natural := 20;
+ constant ZERO_ADDR_MEM : unsigned(LG_MAX_SIZE*2 downto 0) := "000000000000000000000";
+
+ -- This values must not be changed.
+ constant MEM_DATA_WIDTH : natural := 32;
+
+ subtype ogg_int32_t is signed(31 downto 0);
+ subtype uchar_t is unsigned (7 downto 0);
+
+ type mem_64_8bits_t is array (0 to 63) of uchar_t;
+
+-- Fragment Parameters
+ signal HFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal VFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal YStride : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal UVStride : unsigned(LG_MAX_SIZE downto 0);
+ signal YPlaneFragments : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal UVPlaneFragments : unsigned(LG_MAX_SIZE*2-2 downto 0);
+ signal ReconYDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconUDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconVDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal UnitFragmets : unsigned(LG_MAX_SIZE*2 downto 0);
+
+-- FLimits signals
+ signal FLimit : signed(8 downto 0);
+ signal fbv_position : unsigned(8 downto 0);
+ signal fbv_value : signed(9 downto 0);
+
+-- ReconPixelIndex signals and constants
+ constant RPI_DATA_WIDTH : positive := 32;
+ constant RPI_POS_WIDTH : positive := 17;
+ signal rpi_position : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal rpi_value : signed(RPI_DATA_WIDTH-1 downto 0);
+
+ signal s_rpi_in_request : std_logic;
+ signal s_rpi_in_valid : std_logic;
+ signal s_rpi_in_data : signed(31 downto 0);
+
+ signal s_rpi_out_requested : std_logic;
+ signal s_rpi_out_valid : std_logic;
+ signal s_rpi_out_data : signed(31 downto 0);
+
+
+-- Memories
+ signal LoopFilterLimits : mem_64_8bits_t;
+
+-- Process Signals
+ signal ThisFrameQualityValue : signed(31 downto 0);
+
+ signal QIndex : unsigned(5 downto 0);
+ signal pli : unsigned(1 downto 0);
+
+ signal FragsAcross : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal FragsDown : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal LineLength : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal LineFragments : unsigned(LG_MAX_SIZE-3 downto 0);
+ signal Fragment : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal dpf_position : unsigned(LG_MAX_SIZE*2 downto 0);
+
+ signal MaxDPFCount : unsigned(LG_MAX_SIZE*2 downto 0);
+
+ signal pixelPtr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal DeltaHorizFilter : signed(3 downto 0);
+
+ signal CountFilter : unsigned(2 downto 0);
+ signal CountColumns : unsigned(2 downto 0);
+
+ signal disp_frag_value : std_logic;
+
+ signal CountMiddles : unsigned(LG_MAX_SIZE*2 downto 0);
+ signal CountMidCols : unsigned(LG_MAX_SIZE*2 downto 0);
+
+-- Memories Signals
+ signal mem_rd_data : signed(31 downto 0);
+ signal mem_rd_valid : std_logic;
+ signal mem_wr_ready : std_logic;
+
+-- FSMs
+ type state_t is (readIn, proc);
+ signal state : state_t;
+
+ type read_state_t is (stt_qTT, stt_lfLim,
+ stt_dispFrag, stt_Others,
+ stt_32bitsData);
+ signal read_state : read_state_t;
+
+
+ type proc_state_t is (stt_ReadMemory, stt_WriteMemory,
+ stt_FindQIndex, stt_CalcFLimit,
+ stt_SelectColor, stt_ApplyFilter,
+ stt_CalcDispFragPos,
+ stt_CallFilterHoriz, stt_CalcFilterHoriz,
+ stt_CallFilterVert, stt_CalcFilterVert,
+ stt_Calc_RPI_Value);
+ signal proc_state : proc_state_t;
+ signal back_proc_state : proc_state_t;
+ signal next_proc_state : proc_state_t;
+
+ type calc_rpi_state_t is (stt_calc_rpi1, stt_calc_rpi2);
+ signal calc_rpi_state : calc_rpi_state_t;
+
+ type set_bound_val_state_t is (stt_SetBVal1, stt_SetBVal2, stt_SetBVal3, stt_SetBVal4);
+ signal set_bound_val_state : set_bound_val_state_t;
+
+ type calc_filter_state_t is (stt_CalcFilter1, stt_CalcFilter2,
+ stt_CalcFilter3);
+ signal calc_filter_state : calc_filter_state_t;
+
+
+ type apply_filter_state_t is (stt_ApplyFilter_1, stt_ApplyFilter_2,
+ stt_ApplyFilter_3, stt_ApplyFilter_4,
+ stt_ApplyFilter_5, stt_ApplyFilter_6,
+ stt_ApplyFilter_7, stt_ApplyFilter_8,
+ stt_ApplyFilter_9, stt_ApplyFilter_10,
+ stt_ApplyFilter_11, stt_ApplyFilter_12,
+ stt_ApplyFilter_13, stt_ApplyFilter_14,
+ stt_ApplyFilter_15, stt_ApplyFilter_16,
+ stt_ApplyFilter_17, stt_ApplyFilter_18,
+ stt_ApplyFilter_19, stt_ApplyFilter_20,
+ stt_ApplyFilter_21, stt_ApplyFilter_22,
+ stt_ApplyFilter_23, stt_ApplyFilter_24,
+ stt_ApplyFilter_25, stt_ApplyFilter_26,
+ stt_ApplyFilter_27, stt_ApplyFilter_28,
+ stt_ApplyFilter_29, stt_ApplyFilter_30,
+ stt_ApplyFilter_31, stt_ApplyFilter_32,
+ stt_ApplyFilter_33, stt_ApplyFilter_34);
+ signal apply_filter_state : apply_filter_state_t;
+ signal next_apply_filter_state : apply_filter_state_t;
+
+
+ type disp_frag_state_t is (stt_DispFrag1, stt_DispFrag2,
+ stt_DispFrag3, stt_DispFrag4,
+ stt_DispFrag5, stt_DispFrag6,
+ stt_DispFrag7, stt_DispFrag8,
+ stt_DispFrag9, stt_DispFrag10,
+ stt_DispFrag11, stt_DispFrag12,
+ stt_DispFrag13, stt_DispFrag14,
+ stt_DispFrag15, stt_DispFrag16,
+ stt_DispFrag17, stt_DispFrag18,
+ stt_DispFrag19, stt_DispFrag20,
+ stt_DispFrag21, stt_DispFrag22);
+
+ signal disp_frag_state : disp_frag_state_t;
+ signal next_disp_frag_state : disp_frag_state_t;
+
+ type calc_disp_frag_state_t is (stt_CalcDispFrag1,
+ stt_CalcDispFrag2,
+ stt_CalcDispFrag3);
+ signal calc_disp_frag_state : calc_disp_frag_state_t;
+
+-- Handshake
+ signal count : integer range 0 to 2097151;
+
+ signal s_in_request : std_logic;
+
+ signal s_in_sem_request : std_logic;
+ signal s_out_sem_valid : std_logic;
+ signal s_out_done : std_logic;
+
+ signal lfr_OffSet : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+ constant NULL_24bits : signed(23 downto 0) := "000000000000000000000000";
+ constant NULL_32bits : signed(31 downto 0) := x"00000000";
+ constant MAX_32bits : signed(31 downto 0) := x"11111111";
+
+ constant QTT_DEPTH : positive := 64;
+ constant QTT_DATA_WIDTH : positive := 32;
+ constant QTT_ADDR_WIDTH : positive := 6;
+
+ constant DPF_DEPTH : positive := 57;
+ constant DPF_DATA_WIDTH : positive := 32;
+ constant DPF_ADDR_WIDTH : positive := 6;
+
+-- Memories
+ signal qtt_wr_e : std_logic;
+ signal qtt_wr_addr : unsigned(QTT_ADDR_WIDTH-1 downto 0);
+ signal qtt_wr_data : signed(QTT_DATA_WIDTH-1 downto 0);
+ signal qtt_rd_addr : unsigned(QTT_ADDR_WIDTH-1 downto 0);
+ signal qtt_rd_data : signed(QTT_DATA_WIDTH-1 downto 0);
+
+ type mem4bytes_t is array (0 to 3) of uchar_t;
+ signal Pixel : mem4bytes_t;
+ type lfr_array_2_t is array (0 to 1) of ogg_int32_t;
+ signal lfr_datas : lfr_array_2_t;
+ type lfr_pos_pixels_t is array (0 to 1) of unsigned(1 downto 0);
+ signal lfr_pos_pixels : lfr_pos_pixels_t;
+
+ signal dpf_wr_e : std_logic;
+ signal dpf_wr_addr : unsigned(DPF_ADDR_WIDTH-1 downto 0);
+ signal dpf_wr_data : signed(DPF_DATA_WIDTH-1 downto 0);
+ signal dpf_rd_addr : unsigned(DPF_ADDR_WIDTH-1 downto 0);
+ signal dpf_rd_data : signed(DPF_DATA_WIDTH-1 downto 0);
+
+
+-- signal T_Pixel1 : ogg_int32_t;
+-- signal T_Pixel2 : ogg_int32_t;
+
+-- signal applyfilter_states : integer;
+-- signal dispfragstates_states : integer;
+
+
+begin -- a_LoopFilter
+
+ in_request <= s_in_request;
+ in_sem_request <= s_in_sem_request;
+ out_sem_valid <= s_out_sem_valid;
+ out_done <= s_out_done;
+
+ mem_64_int32: tsyncram
+ generic map (QTT_DEPTH, QTT_DATA_WIDTH, QTT_ADDR_WIDTH)
+ port map (clk, qtt_wr_e, qtt_wr_addr, qtt_wr_data, qtt_rd_addr, qtt_rd_data);
+
+ mem_512_int32_1: tsyncram
+ generic map (DPF_DEPTH, DPF_DATA_WIDTH, DPF_ADDR_WIDTH)
+ port map (clk, dpf_wr_e, dpf_wr_addr, dpf_wr_data, dpf_rd_addr, dpf_rd_data);
+
+ lflimits0: lflimits
+ port map (fbv_position, FLimit, fbv_value);
+
+ rpi0: reconpixelindex
+ port map (Clk => Clk,
+ Reset_n => Reset_n,
+ in_request => s_rpi_out_requested,
+ in_valid => s_rpi_out_valid,
+ in_data => s_rpi_out_data,
+
+ out_requested => s_rpi_in_request,
+ out_valid => s_rpi_in_valid,
+ out_data => s_rpi_in_data);
+
+
+ RPI_HandShake: process (count, in_data, in_valid,
+ state, read_state, proc_state,
+ calc_rpi_state, rpi_position,
+ s_in_request)
+ begin -- process RPI_HandShake
+ s_rpi_out_data <= x"00000000";
+ s_rpi_out_valid <= '0';
+ if (s_in_request = '1') then
+ if (state = readIn and read_state = stt_32bitsData) then
+ if (count >=0 and count <=8) then
+ s_rpi_out_data <= in_data;
+ s_rpi_out_valid <= in_valid;
+ end if;
+ end if;
+ else
+ if (state = proc and
+ proc_state = stt_Calc_RPI_Value and
+ calc_rpi_state = stt_calc_rpi1) then
+ s_rpi_out_data <= resize(signed('0'&rpi_position), 32);
+ s_rpi_out_valid <= '1';
+ end if;
+ end if;
+ end process RPI_HandShake;
+
+
+ process (clk)
+-------------------------------------------------------------------------------
+-- Procedures called when state is readIn
+-------------------------------------------------------------------------------
+ procedure Read32bitsData is
+ begin
+-- assert false report "in_data = "&integer'image(to_integer(in_data)) severity note;
+ if (count = 0) then
+ HFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ count <= count + 1;
+ elsif (count = 1) then
+ YPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2 downto 0));
+ count <= count + 1;
+ elsif (count = 2) then
+ YStride <= unsigned(in_data(LG_MAX_SIZE+1 downto 0));
+ count <= count + 1;
+ elsif (count = 3) then
+ UVPlaneFragments <= unsigned(in_data(LG_MAX_SIZE*2-2 downto 0));
+ count <= count + 1;
+ elsif (count = 4) then
+ UVStride <= unsigned(in_data(LG_MAX_SIZE downto 0));
+ count <= count + 1;
+ elsif (count = 5) then
+ VFragments <= unsigned(in_data(LG_MAX_SIZE-3 downto 0));
+ count <= count + 1;
+ elsif (count = 6) then
+ ReconYDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ elsif (count = 7) then
+ ReconUDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ elsif (count = 8) then
+ ReconVDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ count <= count + 1;
+ else
+ assert false report "UnitFragments = "&integer'image(to_integer(in_data)) severity note;
+ UnitFragmets <= unsigned(in_data(LG_MAX_SIZE*2 downto 0));
+
+ MaxDPFCount <= SHIFT_RIGHT(
+ unsigned(in_data(LG_MAX_SIZE*2 downto 0)), 5) + 1;
+ if (in_data(4 downto 0) = "00000") then
+ MaxDPFCount <= SHIFT_RIGHT(
+ unsigned(in_data(LG_MAX_SIZE*2 downto 0)), 5);
+ end if;
+ read_state <= stt_qTT;
+ count <= 0;
+ end if;
+ end procedure Read32bitsData;
+
+-------------------------------------------------------------------------------
+-- Procedure that receives the QThreashTable matrice and keep the data
+-- in a SRAM memory
+-------------------------------------------------------------------------------
+ procedure QThreTab is
+ begin
+ qtt_wr_e <= '1';
+ qtt_wr_data <= in_data;
+ qtt_wr_addr <= qtt_wr_addr + 1;
+
+ if (count = 0) then
+ qtt_wr_addr <= "000000";
+ count <= count + 1;
+ elsif (count = 63) then
+ read_state <= stt_lfLim;
+ count <= 0;
+ -- on next state must set qtt_wr_e to 0
+ else
+ count <= count + 1;
+ end if;
+ end procedure QThreTab;
+
+-------------------------------------------------------------------------------
+-- Procedure that receives the loop filter limits values and keep the data
+-- in an internal memory
+-------------------------------------------------------------------------------
+ procedure LfLim is
+ begin
+ qtt_wr_e <= '0';
+
+ LoopFilterLimits(count + 3) <= unsigned(in_data(7 downto 0));
+ LoopFilterLimits(count + 2) <= unsigned(in_data(15 downto 8));
+ LoopFilterLimits(count + 1) <= unsigned(in_data(23 downto 16));
+ LoopFilterLimits(count) <= unsigned(in_data(31 downto 24));
+ if(count = 60)then
+ read_state <= stt_dispFrag;
+ count <= 0;
+ else
+ count <= count + 4;
+ end if;
+ end procedure LfLim;
+
+-------------------------------------------------------------------------------
+-- Procedure that receives the display fragments matrice and keep the data
+-- in a SRAM memory
+-------------------------------------------------------------------------------
+ procedure DispFrag is
+ begin
+ dpf_wr_e <= '1';
+ dpf_wr_data <= in_data;
+ dpf_wr_addr <= dpf_wr_addr + 1;
+ if (count = 0) then
+ dpf_wr_addr <= "000000";
+ count <= 1;
+ elsif (count = MaxDPFCount - 1) then
+ read_state <= stt_Others;
+ count <= 0;
+ else
+ count <= count + 1;
+ end if;
+ end procedure DispFrag;
+
+-------------------------------------------------------------------------------
+-- Procedure that receives the ThisFrameQualityValue and the Last Reconstructed
+-- Frame offset
+-------------------------------------------------------------------------------
+ procedure ReadOthers is
+ begin
+ if (count = 0) then
+ ThisFrameQualityValue <= in_data;
+ count <= count + 1;
+ else
+ lfr_OffSet <= SHIFT_RIGHT(unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0)), 2);
+ state <= proc;
+ count <= 0;
+ read_state <= stt_dispFrag;
+ proc_state <= stt_FindQIndex;
+ s_in_request <= '0';
+ QIndex <= "111111";
+ end if;
+ end procedure ReadOthers;
+
+-------------------------------------------------------------------------------
+-- Procedure that controls the read state machine
+-------------------------------------------------------------------------------
+ procedure ReadIn is
+ begin
+ s_out_done <= '0';
+ s_in_request <= '1';
+
+ s_out_sem_valid <= '0';
+ s_in_sem_request <= '0';
+ if (s_in_request = '1' and in_valid = '1') then
+
+ case read_state is
+ when stt_qTT => QThreTab;
+ when stt_lfLim => LfLim;
+ when stt_dispFrag => DispFrag;
+ when stt_Others => ReadOthers;
+ when others => Read32bitsData;
+ end case;
+ end if;
+ end procedure ReadIn;
+
+-- *****************************************************
+-- Procedures called when state is proc
+-- *****************************************************
+
+ procedure ReadMemory is
+ begin
+ -- After use the data mem_rd_valid must
+ -- be set to '0'
+ mem_rd_valid <= in_sem_valid;
+ s_in_sem_request <= '1';
+ if (s_in_sem_request = '1' and in_sem_valid = '1') then
+ mem_rd_data <= in_sem_data;
+ s_in_sem_request <= '0';
+ proc_state <= back_proc_state;
+ end if;
+ end procedure ReadMemory;
+
+ procedure WriteMemory is
+ begin
+ if (out_sem_requested = '1') then
+ proc_state <= back_proc_state;
+ mem_wr_ready <= '1';
+ s_out_sem_valid <= '0';
+ end if;
+ end procedure WriteMemory;
+
+ procedure CalcRPIValue is
+ begin
+ case calc_rpi_state is
+ when stt_calc_rpi1 =>
+ -- Wait until ReconPixelIndex can receive the data
+ if (s_rpi_out_requested = '1') then
+ calc_rpi_state <= stt_calc_rpi2;
+ end if;
+
+
+ when others =>
+ -- Wait until ReconPixelIndex returns the value
+ s_rpi_in_request <= '1';
+ if (s_rpi_in_request = '1' and s_rpi_in_valid = '1') then
+ rpi_value <= s_rpi_in_data;
+ s_rpi_in_request <= '0';
+ proc_state <= next_proc_state;
+ end if;
+ end case;
+ end procedure CalcRPIValue;
+
+-------------------------------------------------------------------------------
+-- Initialize QIndex with 63.
+-- For each element i of qtt in decreasing order, if i >= ThisFrameQualityValue
+-- then stop, else subtract one of the QIndex and read the i-1 element of qtt,
+-- until QIndex = 0
+-------------------------------------------------------------------------------
+ procedure FindQIndex is
+ begin
+ if (count = 0) then
+ qtt_rd_addr <= QIndex;
+ count <= 1;
+ elsif (count = 1) then
+ qtt_rd_addr <= QIndex - 1;
+ count <= 2;
+ else
+ if ((QIndex = "000000") or
+ (qtt_rd_data >= ThisFrameQualityValue)) then
+ proc_state <= stt_CalcFLimit;
+ count <= 0;
+ else
+ qtt_rd_addr <= QIndex - 2;
+ QIndex <= QIndex - 1;
+ count <= 2;
+ end if;
+ end if;
+ end procedure FindQIndex;
+
+-------------------------------------------------------------------------------
+-- If LoopFilterLimits[QIndex] is not zero do the loopfiltering in the frame.
+-- The next procedure is SelectColor
+-------------------------------------------------------------------------------
+ procedure CalcFLimit is
+ begin
+ if (LoopFilterLimits(to_integer(QIndex)) /= "00000000000000000000000000000000") then
+ proc_state <= stt_SelectColor;
+ FLimit <= '0' & signed(LoopFilterLimits(to_integer(QIndex)));
+ else
+ pli <= "00";
+ count <= 0;
+ s_out_done <= '1';
+
+ state <= readIn;
+ read_state <= stt_dispFrag;
+ proc_state <= stt_FindQIndex;
+ apply_filter_state <= stt_ApplyFilter_1;
+ calc_filter_state <= stt_CalcFilter1;
+ end if;
+ end procedure CalcFLimit;
+
+-------------------------------------------------------------------------------
+-- Adjust some parameters according the plane of color
+-------------------------------------------------------------------------------
+ procedure SelectColor is
+ begin
+ if (pli = "00") then
+ FragsAcross <= HFragments;
+ LineLength <= YStride;
+ LineFragments <= HFragments;
+ FragsDown <= VFragments;
+ Fragment <= "000000000000000000000";
+ proc_state <= stt_ApplyFilter;
+ disp_frag_state <= stt_DispFrag1;
+ pli <= pli + 1;
+
+ elsif (pli = "01") then
+
+ FragsAcross <= SHIFT_RIGHT(HFragments, 1);
+ LineLength <= '0' & UVStride;
+ LineFragments <= SHIFT_RIGHT(HFragments, 1);
+ FragsDown <= SHIFT_RIGHT(VFragments, 1);
+ Fragment <= YPlaneFragments;
+ proc_state <= stt_ApplyFilter;
+ disp_frag_state <= stt_DispFrag1;
+ pli <= pli + 1;
+
+ elsif (pli = "10") then
+
+ FragsAcross <= SHIFT_RIGHT(HFragments, 1);
+ LineLength <= '0' & UVStride;
+ LineFragments <= SHIFT_RIGHT(HFragments, 1);
+ FragsDown <= SHIFT_RIGHT(VFragments, 1);
+ Fragment <= YPlaneFragments + UVPlaneFragments;
+ proc_state <= stt_ApplyFilter;
+ disp_frag_state <= stt_DispFrag1;
+ pli <= pli + 1;
+ else
+ assert false report "SelectColor 4" severity note;
+ pli <= "00";
+ count <= 0;
+ s_out_done <= '1';
+
+ state <= readIn;
+ read_state <= stt_dispFrag;
+ proc_state <= stt_FindQIndex;
+ apply_filter_state <= stt_ApplyFilter_1;
+ calc_filter_state <= stt_CalcFilter1;
+ end if;
+ end procedure SelectColor;
+
+
+ procedure CallFilterHoriz is
+ variable fourPixels : signed(MEM_DATA_WIDTH-1 downto 0);
+ variable memPosPixel : unsigned(1 downto 0);
+ variable numPixel : signed(RPI_DATA_WIDTH-1 downto 0);
+
+ begin
+ numPixel := rpi_value +
+ DeltaHorizFilter +
+ ('0' & signed(pixelPtr) + count);
+ memPosPixel := unsigned(numPixel(1 downto 0));
+
+ -- When use the data mem_rd_valid must
+ -- be set to '0'
+ if (mem_rd_valid = '0') then
+ s_in_sem_request <= '1';
+ in_sem_addr <= lfr_OffSet +
+ resize(
+ SHIFT_RIGHT('0' & unsigned(numPixel), 2)
+ , MEM_ADDR_WIDTH
+ );
+ back_proc_state <= stt_CallFilterHoriz;
+ proc_state <= stt_ReadMemory;
+ else
+ mem_rd_valid <= '0';
+ fourPixels := (SHIFT_RIGHT(
+ mem_rd_data,
+ 24 -
+ to_integer(memPosPixel) * 8));
+ Pixel(count) <= unsigned(fourPixels(7 downto 0));
+
+ if (count = 1 or count = 2) then
+ -- Saves the second or third pixel data slot and
+ -- their positions in the slot
+ lfr_datas(count - 1) <= mem_rd_data;
+ lfr_pos_pixels(count - 1) <= memPosPixel;
+ end if;
+ if (count = 3) then
+ fbv_position <= resize(unsigned(
+ 256 +
+ SHIFT_RIGHT(
+ ("0000" &
+ signed(Pixel(0))) -
+ (("0000" &
+ signed(Pixel(1))) * 3) +
+ (("0000" &
+ signed(Pixel(2))) * 3) -
+ ("0000" &
+ signed(fourPixels(7 downto 0))) + 4
+ , 3)), 9);
+
+ count <= 0;
+ proc_state <= stt_CalcFilterHoriz;
+ else
+ count <= count + 1;
+ end if;
+ end if;
+ end procedure CallFilterHoriz;
+
+ procedure CalcFilterHoriz is
+ variable Pixel1 : ogg_int32_t;
+ variable Pixel2 : ogg_int32_t;
+ variable newPixel : uchar_t;
+
+ begin
+ if (calc_filter_state = stt_CalcFilter1) then
+
+ Pixel1 := NULL_24bits &
+ signed(Pixel(1)) + fbv_value;
+-- T_Pixel1 <= Pixel1;
+
+ out_sem_addr <= lfr_OffSet +
+ resize(
+ SHIFT_RIGHT(
+ '0' &
+ unsigned(
+ rpi_value +
+ DeltaHorizFilter +
+ ('0' & signed(pixelPtr)) + 1)
+ ,2
+ ), MEM_ADDR_WIDTH
+ );
+
+ if (Pixel1 < "00000000000000000000000000000000") then
+ newPixel := "00000000";
+ elsif (Pixel1 > "00000000000000000000000011111111") then
+ newPixel := "11111111";
+ else
+ newPixel := unsigned(Pixel1(7 downto 0));
+ end if;
+
+ case lfr_pos_pixels(0) is
+ when "00" =>
+ out_sem_data <= signed(newPixel) &
+ lfr_datas(0)(23 downto 0);
+ when "01" =>
+ out_sem_data <= lfr_datas(0)(31 downto 24) &
+ signed(newPixel) &
+ lfr_datas(0)(15 downto 0);
+ when "10" =>
+ out_sem_data <= lfr_datas(0)(31 downto 16) &
+ signed(newPixel) &
+ lfr_datas(0)(7 downto 0);
+ when others =>
+ out_sem_data <= lfr_datas(0)(31 downto 8) &
+ signed(newPixel);
+ end case;
+
+ s_out_sem_valid <= '1';
+ calc_filter_state <= stt_CalcFilter2;
+ back_proc_state <= stt_CalcFilterHoriz;
+ proc_state <= stt_WriteMemory;
+
+ elsif (calc_filter_state = stt_CalcFilter2) then
+ Pixel2 := NULL_24bits &
+ signed(Pixel(2)) - fbv_value;
+
+-- T_Pixel2 <= Pixel2;
+
+ out_sem_addr <= lfr_OffSet +
+ resize(
+ SHIFT_RIGHT(
+ '0' &
+ unsigned(
+ rpi_value +
+ DeltaHorizFilter +
+ ('0' & signed(pixelPtr)) + 2)
+ ,2
+ ), MEM_ADDR_WIDTH
+ );
+
+
+ if (Pixel2 < "00000000000000000000000000000000") then
+ newPixel := "00000000";
+ elsif (Pixel2 > "00000000000000000000000011111111") then
+ newPixel := "11111111";
+ else
+ newPixel := unsigned(Pixel2(7 downto 0));
+ end if;
+
+ case lfr_pos_pixels(1) is
+ when "00" =>
+ out_sem_data <= signed(newPixel) &
+ lfr_datas(1)(23 downto 0);
+ when "01" =>
+ out_sem_data <= lfr_datas(1)(31 downto 24) &
+ signed(newPixel) &
+ lfr_datas(1)(15 downto 0);
+ when "10" =>
+ out_sem_data <= lfr_datas(1)(31 downto 16) &
+ signed(newPixel) &
+ lfr_datas(1)(7 downto 0);
+ when others =>
+ out_sem_data <= lfr_datas(1)(31 downto 8) &
+ signed(newPixel);
+ end case;
+
+ s_out_sem_valid <= '1';
+ calc_filter_state <= stt_CalcFilter3;
+ back_proc_state <= stt_CalcFilterHoriz;
+ proc_state <= stt_WriteMemory;
+
+ else
+
+ if (CountFilter = "111") then
+ proc_state <= stt_ApplyFilter;
+ apply_filter_state <= next_apply_filter_state; -- Next state
+ pixelPtr <= "00000000000000000000";
+ CountFilter <= "000";
+ else
+ pixelPtr <= pixelPtr + LineLength; -- Next Row
+ proc_state <= stt_CallFilterHoriz;
+ CountFilter <= CountFilter + 1;
+ end if;
+ calc_filter_state <= stt_CalcFilter1;
+ end if;
+ end procedure CalcFilterHoriz;
+
+
+ procedure CallFilterVert is
+ variable fourPixels : signed(MEM_DATA_WIDTH-1 downto 0);
+ variable memPosPixel : unsigned(1 downto 0);
+ variable numPixel : signed(RPI_DATA_WIDTH-1 downto 0);
+ variable posLine : signed(2 downto 0);
+ begin
+ if (count = 0) then
+ posLine := "110";
+ elsif (count = 1) then
+ posLine := "111";
+ elsif (count = 2) then
+ posLine := "000";
+ else
+ posLine := "001";
+ end if;
+
+ numPixel := rpi_value +
+ (signed('0' & LineLength)*posLine) +
+ ('0' & signed(CountColumns));
+ memPosPixel := unsigned(numPixel(1 downto 0));
+
+ -- When use the data mem_rd_valid must
+ -- be set to '0'
+
+ if (mem_rd_valid = '0') then
+ s_in_sem_request <= '1';
+ in_sem_addr <= lfr_OffSet +
+ resize(
+ SHIFT_RIGHT('0' & unsigned(numPixel), 2)
+ , MEM_ADDR_WIDTH
+ );
+
+ if (to_integer(lfr_OffSet +
+ resize(
+ SHIFT_RIGHT('0' & unsigned(numPixel), 2)
+ , MEM_ADDR_WIDTH
+ )) = 1530) then
+ end if;
+
+
+ back_proc_state <= stt_CallFilterVert;
+ proc_state <= stt_ReadMemory;
+
+ else
+ mem_rd_valid <= '0';
+
+ fourPixels := (SHIFT_RIGHT(
+ mem_rd_data,
+ 24 -
+ to_integer(memPosPixel) * 8));
+
+ Pixel(count) <= unsigned(fourPixels(7 downto 0));
+
+ if (count = 1 or count = 2) then
+ -- Saves the second or third pixel data slot and
+ -- their positions in the slot
+ lfr_datas(count - 1) <= mem_rd_data;
+ lfr_pos_pixels(count - 1) <= memPosPixel;
+ end if;
+ if (count = 3) then
+ fbv_position <= resize(unsigned(
+ 256 +
+ SHIFT_RIGHT(
+ ("0000" &
+ signed(Pixel(0))) -
+ (("0000" &
+ signed(Pixel(1))) * 3) +
+ (("0000" &
+ signed(Pixel(2))) * 3) -
+ ("0000" &
+ signed(fourPixels(7 downto 0))) + 4
+ , 3)), 9);
+ count <= 0;
+ proc_state <= stt_CalcFilterVert;
+ else
+ count <= count + 1;
+ end if;
+ end if;
+ end procedure CallFilterVert;
+
+ procedure CalcFilterVert is
+ variable Pixel1 : ogg_int32_t;
+ variable Pixel2 : ogg_int32_t;
+ variable newPixel : uchar_t;
+
+ begin
+
+ if (calc_filter_state = stt_CalcFilter1) then
+
+ Pixel1 := (NULL_24bits &
+ signed(Pixel(1))) + fbv_value;
+-- T_Pixel1 <= Pixel1;
+ out_sem_addr <= lfr_OffSet +
+ resize(
+ SHIFT_RIGHT(
+ '0' &
+ unsigned(
+ rpi_value -
+ ('0' & signed(LineLength)) +
+ ('0' & signed(CountColumns)))
+ ,2
+ ), MEM_ADDR_WIDTH
+ );
+
+ if (Pixel1 < "00000000000000000000000000000000") then
+ newPixel := "00000000";
+ elsif (Pixel1 > "00000000000000000000000011111111") then
+ newPixel := "11111111";
+ else
+ newPixel := unsigned(Pixel1(7 downto 0));
+ end if;
+
+ case lfr_pos_pixels(0) is
+ when "00" =>
+ out_sem_data <= signed(newPixel) &
+ lfr_datas(0)(23 downto 0);
+ when "01" =>
+ out_sem_data <= lfr_datas(0)(31 downto 24) &
+ signed(newPixel) &
+ lfr_datas(0)(15 downto 0);
+ when "10" =>
+ out_sem_data <= lfr_datas(0)(31 downto 16) &
+ signed(newPixel) &
+ lfr_datas(0)(7 downto 0);
+ when others =>
+ out_sem_data <= lfr_datas(0)(31 downto 8) &
+ signed(newPixel);
+ end case;
+
+ s_out_sem_valid <= '1';
+ calc_filter_state <= stt_CalcFilter2;
+ back_proc_state <= stt_CalcFilterVert;
+ proc_state <= stt_WriteMemory;
+
+ elsif (calc_filter_state = stt_CalcFilter2) then
+
+ Pixel2 := (NULL_24bits &
+ signed(Pixel(2))) - fbv_value;
+-- T_Pixel2 <= Pixel2;
+
+ out_sem_addr <= lfr_OffSet +
+ resize(
+ SHIFT_RIGHT(
+ '0' &
+ unsigned(
+ rpi_value +
+ ('0' & signed(CountColumns)))
+ ,2
+ ), MEM_ADDR_WIDTH
+ );
+
+ if (Pixel2 < "00000000000000000000000000000000") then
+ newPixel := "00000000";
+ elsif (Pixel2 > "00000000000000000000000011111111") then
+ newPixel := "11111111";
+ else
+ newPixel := unsigned(Pixel2(7 downto 0));
+ end if;
+
+ case lfr_pos_pixels(1) is
+ when "00" =>
+ out_sem_data <= signed(newPixel) &
+ lfr_datas(1)(23 downto 0);
+ when "01" =>
+ out_sem_data <= lfr_datas(1)(31 downto 24) &
+ signed(newPixel) &
+ lfr_datas(1)(15 downto 0);
+ when "10" =>
+ out_sem_data <= lfr_datas(1)(31 downto 16) &
+ signed(newPixel) &
+ lfr_datas(1)(7 downto 0);
+ when others =>
+ out_sem_data <= lfr_datas(1)(31 downto 8) &
+ signed(newPixel);
+ end case;
+
+ s_out_sem_valid <= '1';
+ calc_filter_state <= stt_CalcFilter3;
+ back_proc_state <= stt_CalcFilterVert;
+ proc_state <= stt_WriteMemory;
+
+ else
+
+ if (CountFilter = "111") then
+ proc_state <= stt_ApplyFilter;
+ apply_filter_state <= next_apply_filter_state; -- Next state
+ CountFilter <= "000";
+ CountColumns <= "000";
+ else
+ CountColumns <= CountColumns + 1;
+ proc_state <= stt_CallFilterVert;
+ CountFilter <= CountFilter + 1;
+ end if;
+ calc_filter_state <= stt_CalcFilter1;
+ end if;
+ end procedure CalcFilterVert;
+
+
+ procedure CalcDispFragPos is
+ begin
+ if (calc_disp_frag_state = stt_CalcDispFrag1) then
+ -- Wait display_fragments memory
+ calc_disp_frag_state <= stt_CalcDispFrag2;
+
+ else
+ disp_frag_value <= dpf_rd_data(31 - to_integer(dpf_position(4 downto 0)));
+ calc_disp_frag_state <= stt_CalcDispFrag1;
+ proc_state <= stt_ApplyFilter;
+ apply_filter_state <= next_apply_filter_state; -- Next state
+ disp_frag_state <= next_disp_frag_state;
+ end if;
+ end procedure CalcDispFragPos;
+
+
+ procedure ApplyFilter is
+ variable NextFragment : unsigned(LG_MAX_SIZE*2 downto 0);
+ begin
+
+ if (apply_filter_state = stt_ApplyFilter_1) then
+-- applyfilter_states <= 1;
+ -- ******************************************************
+ -- First Row
+ -- ******************************************************
+ -- First column coditions
+ -- only do 2 prediction if fragment coded and on non intra
+ -- or if all fragments are intra
+ if (disp_frag_state = stt_DispFrag1) then
+-- dispfragstates_states <= 1;
+ -- dpf_rd_addr <= resize(SHIFT_RIGHT(Fragment,5), DPF_ADDR_WIDTH);
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_1;
+ next_disp_frag_state <= stt_DispFrag2;
+ else
+ if (disp_frag_value = '1') then
+ apply_filter_state <= stt_ApplyFilter_34;
+ else
+ apply_filter_state <= stt_ApplyFilter_3;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_34) then
+-- applyfilter_states <= 34;
+ -- Filter right hand border only if the block to the right
+ -- is not coded
+ if (disp_frag_state = stt_DispFrag2) then
+-- dispfragstates_states <= 2;
+ NextFragment := Fragment + 1;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+ dpf_position <= Fragment + 1;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_34;
+ next_disp_frag_state <= stt_DispFrag3;
+ else
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"6";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_2;
+ else
+ apply_filter_state <= stt_ApplyFilter_2;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_2) then
+-- applyfilter_states <= 2;
+ -- Bottom done if next row set
+ if (disp_frag_state = stt_DispFrag3) then
+ NextFragment := Fragment + LineFragments;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+ dpf_position <= Fragment + LineFragments;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_2;
+ next_disp_frag_state <= stt_DispFrag4;
+ else
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment + LineFragments, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_3;
+ else
+ apply_filter_state <= stt_ApplyFilter_3;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_3) then
+-- applyfilter_states <= 3;
+ Fragment <= Fragment + 1;
+ CountMiddles <= '0' & x"00001";
+ apply_filter_state <= stt_ApplyFilter_4;
+ disp_frag_state <= stt_DispFrag4;
+
+ elsif (apply_filter_state = stt_ApplyFilter_4) then
+
+ if (CountMiddles < FragsAcross - 1) then
+
+ -- Middle Columns
+
+ if (disp_frag_state = stt_DispFrag4) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_4;
+ next_disp_frag_state <= stt_DispFrag5;
+
+ else
+
+ if (disp_frag_value = '1') then
+ -- Filter Left edge always
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"E";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+
+ next_apply_filter_state <= stt_ApplyFilter_5;
+ else
+ apply_filter_state <= stt_ApplyFilter_7; -- Increment CountMiddles
+ end if;
+ end if;
+ else
+ apply_filter_state <= stt_ApplyFilter_8;
+ disp_frag_state <= stt_DispFrag7;
+ end if;
+
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_5) then
+
+ -- Enter here only if (CountMiddles < FragsAcross - 1) is true
+ -- and display_fragments(Fragment) is not zero
+ if (disp_frag_state = stt_DispFrag5) then
+ NextFragment := Fragment + 1;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + 1;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_5;
+ next_disp_frag_state <= stt_DispFrag6;
+
+ else
+
+ if (disp_frag_value = '0') then
+
+ -- Filter right hand border only if the block to the right is
+ -- not coded
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"6";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_6;
+
+ else
+ apply_filter_state <= stt_ApplyFilter_6;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_6) then
+
+ -- Enter here only if (CountMiddles < FragsAcross - 1) is true
+ -- and display_fragments(Fragment) is not zero
+ if (disp_frag_state = stt_DispFrag6) then
+ NextFragment := Fragment + LineFragments;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + LineFragments;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_6;
+ next_disp_frag_state <= stt_DispFrag7;
+
+ else
+
+ if (disp_frag_value = '0') then
+
+ -- Bottom done if next row set
+ rpi_position <= resize(Fragment + LineFragments, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_7;
+ else
+ apply_filter_state <= stt_ApplyFilter_7;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_7) then
+
+ CountMiddles <= CountMiddles + 1;
+ Fragment <= Fragment + 1;
+ apply_filter_state <= stt_ApplyFilter_4;
+ disp_frag_state <= stt_DispFrag4;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_8) then
+
+ -- ******************************************************
+ -- Last Column
+ -- ******************************************************
+ if (disp_frag_state = stt_DispFrag7) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_8;
+ next_disp_frag_state <= stt_DispFrag8;
+
+ else
+
+ if (disp_frag_value = '1') then
+ -- Filter Left edge always
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"E";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_9;
+ else
+ apply_filter_state <= stt_ApplyFilter_10;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_9) then
+
+ if (disp_frag_state = stt_DispFrag8) then
+ NextFragment := Fragment + LineFragments;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + LineFragments;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_9;
+ next_disp_frag_state <= stt_DispFrag9;
+
+ else
+ if (disp_frag_value = '0') then
+ -- Bottom done if next row set
+ rpi_position <= resize(Fragment + LineFragments, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_10;
+ else
+ apply_filter_state <= stt_ApplyFilter_10;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_10) then
+
+ Fragment <= Fragment + 1;
+ CountMiddles <= '0' & x"00001";
+ apply_filter_state <= stt_ApplyFilter_11;
+ disp_frag_state <= stt_DispFrag9;
+
+ elsif (apply_filter_state = stt_ApplyFilter_11) then
+
+
+ -- ******************************************************
+ -- Middle Rows
+ -- ******************************************************
+ if (CountMiddles < FragsDown - 1) then
+ -- first column conditions
+ -- only do 2 prediction if fragment coded and on non intra or if
+ -- all fragments are intra */
+ if (disp_frag_state = stt_DispFrag9) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_11;
+ next_disp_frag_state <= stt_DispFrag10;
+ else
+ if (disp_frag_value = '1') then
+ -- TopRow is always done
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_12;
+ else
+ apply_filter_state <= stt_ApplyFilter_14; -- Do middle columns
+ end if;
+ end if;
+ else
+ apply_filter_state <= stt_ApplyFilter_24; -- End "Loop"
+ disp_frag_state <= stt_DispFrag17;
+ end if;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_12) then
+
+ -- Enter here only if (CountMiddles < FragsDown - 1) is true
+ -- and display_fragments(Fragment) is not zero
+ if (disp_frag_state = stt_DispFrag10) then
+ NextFragment := Fragment + 1;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + 1;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_12;
+ next_disp_frag_state <= stt_DispFrag11;
+ else
+
+ if (disp_frag_value = '0') then
+ -- Filter right hand border only if the block to the right is
+ -- not coded
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"6";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_13;
+ else
+ apply_filter_state <= stt_ApplyFilter_13;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_13) then
+
+ -- Enter here only if (CountMiddles < FragsDown - 1) is true
+ -- and display_fragments(Fragment) is not zero
+ if (disp_frag_state = stt_DispFrag11) then
+ NextFragment := Fragment + LineFragments;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + LineFragments;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_13;
+ next_disp_frag_state <= stt_DispFrag12;
+ else
+
+ if (disp_frag_value = '0') then
+ -- Bottom done if next row set
+ rpi_position <= resize(Fragment + LineFragments, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_14;
+ else
+ apply_filter_state <= stt_ApplyFilter_14;
+ end if;
+ end if;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_14) then
+
+ Fragment <= Fragment + 1; -- Increment position
+ CountMidCols <= '0' & x"00001"; -- Initialize Counter
+ apply_filter_state <= stt_ApplyFilter_15;
+ disp_frag_state <= stt_DispFrag12;
+
+ elsif (apply_filter_state = stt_ApplyFilter_15) then
+
+ -- ******************************************************
+ -- Middle Columns inside Middle Rows
+ -- ******************************************************
+ if (CountMidCols < FragsAcross - 1) then
+
+ if (disp_frag_state = stt_DispFrag12) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_15;
+ next_disp_frag_state <= stt_DispFrag13;
+ else
+ if (disp_frag_value = '1') then
+ -- Filter Left edge always
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"E";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_16;
+ else
+ apply_filter_state <= stt_ApplyFilter_19; -- Increment CountMidCols
+ end if;
+ end if;
+ else
+
+ apply_filter_state <= stt_ApplyFilter_20; -- End "Loop" and
+ -- do Last Column
+ disp_frag_state <= stt_DispFrag15;
+ end if;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_16) then
+
+ -- Enter here only if (CountMidCols < FragsAcross - 1) is true
+ -- and display_fragments(Fragment) is not zero
+
+ -- TopRow is always done
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_17;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_17) then
+
+ -- Enter here only if (CountMidCols < FragsAcross - 1) is true
+ -- and display_fragments(Fragment) is not zero
+
+ -- Filter right hand border only if the block to the right
+ -- is not coded
+ if (disp_frag_state = stt_DispFrag13) then
+ NextFragment := Fragment + 1;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + 1;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_17;
+ next_disp_frag_state <= stt_DispFrag14;
+ else
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"6";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_18;
+ else
+ apply_filter_state <= stt_ApplyFilter_18;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_18) then
+
+ -- Enter here only if (CountMidCols < FragsAcross - 1) is true
+ -- and display_fragments(Fragment) is not zero
+
+ -- Bottom done if next row set
+ if (disp_frag_state = stt_DispFrag14) then
+ NextFragment := Fragment + LineFragments;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + LineFragments;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_18;
+ next_disp_frag_state <= stt_DispFrag15;
+ else
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment + LineFragments, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_19;
+ else
+ apply_filter_state <= stt_ApplyFilter_19;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_19) then
+
+ CountMidCols <= CountMidCols + 1;
+ Fragment <= Fragment + 1;
+ apply_filter_state <= stt_ApplyFilter_15;
+ disp_frag_state <= stt_DispFrag12;
+
+ elsif (apply_filter_state = stt_ApplyFilter_20) then
+
+ -- Last Column
+
+ if (disp_frag_state = stt_DispFrag15) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_20;
+ next_disp_frag_state <= stt_DispFrag16;
+ else
+ if (disp_frag_value = '1') then
+ -- Filter Left edge always
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"E";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_21;
+ else
+ apply_filter_state <= stt_ApplyFilter_23;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_21) then
+
+ -- Enter here only if display_fragments(Fragment) not zero
+
+ -- TopRow is always done
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_22;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_22) then
+ -- Enter here only if display_fragments(Fragment) not zero
+
+
+ -- Bottom done if next row set
+ if (disp_frag_state = stt_DispFrag16) then
+ NextFragment := Fragment + LineFragments;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + LineFragments;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_22;
+ next_disp_frag_state <= stt_DispFrag17;
+ else
+
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment + LineFragments, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_23;
+ else
+ apply_filter_state <= stt_ApplyFilter_23;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_23) then
+
+ Fragment <= Fragment + 1;
+ CountMiddles <= CountMiddles + 1;
+ apply_filter_state <= stt_ApplyFilter_11;
+ disp_frag_state <= stt_DispFrag9;
+
+ elsif (apply_filter_state = stt_ApplyFilter_24) then
+
+ -- ******************************************************
+ -- Last Row
+ -- ******************************************************
+
+ -- First column conditions
+ -- Only do 2 prediction if fragment coded and on non intra or if
+ -- all fragments are intra */
+ if (disp_frag_state = stt_DispFrag17) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_24;
+ next_disp_frag_state <= stt_DispFrag18;
+ else
+
+ if (disp_frag_value = '1') then
+ -- TopRow is always done
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_25;
+ else
+ apply_filter_state <= stt_ApplyFilter_26;
+ end if;
+ end if;
+ elsif (apply_filter_state = stt_ApplyFilter_25) then
+
+ -- Enter here only if display_fragments(Fragment) is not zero
+
+ -- Filter right hand border only if the block to the right
+ -- is not coded
+ if (disp_frag_state = stt_DispFrag18) then
+ NextFragment := Fragment + 1;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + 1;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_25;
+ next_disp_frag_state <= stt_DispFrag19;
+ else
+
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"6";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_26;
+ else
+ apply_filter_state <= stt_ApplyFilter_26;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_26) then
+
+ Fragment <= Fragment + 1;
+ CountMiddles <= '0' & x"00001";
+ apply_filter_state <= stt_ApplyFilter_27;
+ disp_frag_state <= stt_DispFrag19;
+
+ elsif (apply_filter_state = stt_ApplyFilter_27) then
+
+ if (CountMiddles < FragsAcross - 1) then
+ -- Middle Columns
+ if (disp_frag_state = stt_DispFrag19) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_27;
+ next_disp_frag_state <= stt_DispFrag20;
+ else
+ if (disp_frag_value = '1') then
+ -- Filter Left edge always
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"E";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_28;
+ else
+ apply_filter_state <= stt_ApplyFilter_30; -- Increment CountMiddles
+ end if;
+ end if;
+ else
+ apply_filter_state <= stt_ApplyFilter_31; -- End "Loop"
+ disp_frag_state <= stt_DispFrag21;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_28) then
+
+ -- Enter here only if display_fragments(Fragment) is not zero
+
+ -- TopRow is always done
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_29;
+
+ elsif (apply_filter_state = stt_ApplyFilter_29) then
+
+ -- Enter here only if (CountMidCols < FragsAcross - 1) is true
+ -- and display_fragments(Fragment) is not zero
+
+ -- Filter right hand border only if the block to the right
+ -- is not coded
+ if (disp_frag_state = stt_DispFrag20) then
+ NextFragment := Fragment + 1;
+ dpf_rd_addr <= NextFragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment + 1;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_29;
+ next_disp_frag_state <= stt_DispFrag21;
+ else
+ if (disp_frag_value = '0') then
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ --Horizontal Filter Parameter
+ DeltaHorizFilter <= x"6";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_30;
+ else
+ apply_filter_state <= stt_ApplyFilter_30;
+ end if;
+ end if;
+
+
+ elsif (apply_filter_state = stt_ApplyFilter_30) then
+
+ CountMiddles <= CountMiddles +1;
+ Fragment <= Fragment + 1;
+ apply_filter_state <= stt_ApplyFilter_27;
+ disp_frag_state <= stt_DispFrag19;
+
+ elsif (apply_filter_state = stt_ApplyFilter_31) then
+
+ -- ******************************************************
+ -- Last Column
+ -- ******************************************************
+ if (disp_frag_state = stt_DispFrag21) then
+ dpf_rd_addr <= Fragment((4+DPF_ADDR_WIDTH) downto 5);
+
+ dpf_position <= Fragment;
+ proc_state <= stt_CalcDispFragPos;
+ next_apply_filter_state <= stt_ApplyFilter_31;
+ next_disp_frag_state <= stt_DispFrag22;
+ else
+
+ if (disp_frag_value = '1') then
+ -- Filter Left edge always
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+ -- Horizontal Filter Parameter
+ DeltaHorizFilter <= x"E";
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterHoriz;
+ next_apply_filter_state <= stt_ApplyFilter_32;
+ else
+ apply_filter_state <= stt_ApplyFilter_33;
+ end if;
+ end if;
+
+ elsif (apply_filter_state = stt_ApplyFilter_32) then
+
+ -- Enter here only if display_fragments(Fragment) is not zero
+
+ -- TopRow is always done
+ rpi_position <= resize(Fragment, RPI_POS_WIDTH);
+
+ -- Calculate RPI_Value before continue
+ proc_state <= stt_Calc_RPI_Value;
+ calc_rpi_state <= stt_calc_rpi1;
+ -- Next state after RPI_Value calculation
+ next_proc_state <= stt_CallFilterVert;
+ next_apply_filter_state <= stt_ApplyFilter_33;
+
+
+ --elsif (apply_filter_state = stt_ApplyFilter_33) then
+ else
+
+ proc_state <= stt_SelectColor;
+ apply_filter_state <= stt_ApplyFilter_1;
+ next_disp_frag_state <= stt_DispFrag1;
+ end if;
+ end procedure ApplyFilter;
+
+
+ procedure Proc is
+ begin
+ case proc_state is
+ when stt_ReadMemory => ReadMemory;
+ when stt_WriteMemory => WriteMemory;
+ when stt_Calc_RPI_Value => CalcRPIValue;
+ when stt_FindQIndex => FindQIndex;
+ when stt_CalcFLimit => CalcFLimit;
+ when stt_SelectColor => SelectColor;
+ when stt_ApplyFilter => ApplyFilter;
+ when stt_CalcDispFragPos => CalcDispFragPos;
+ when stt_CallFilterHoriz => CallFilterHoriz;
+ when stt_CalcFilterHoriz => CalcFilterHoriz;
+ when stt_CallFilterVert => CallFilterVert;
+ -- when stt_CalcFilterVert = other
+ when others => CalcFilterVert;
+ end case;
+ end procedure Proc;
+
+ begin -- process
+
+
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ state <= readIn;
+ read_state <= stt_32bitsData;
+ proc_state <= stt_FindQIndex;
+ apply_filter_state <= stt_ApplyFilter_1;
+ calc_filter_state <= stt_CalcFilter1;
+ calc_rpi_state <= stt_calc_rpi1;
+
+ s_in_request <= '0';
+ s_in_sem_request <= '0';
+ count <= 0;
+ pli <= "00";
+ s_out_sem_valid <= '0';
+ s_out_done <= '0';
+
+ mem_rd_valid <= '0';
+
+ CountFilter <= "000";
+ CountColumns <= "000";
+ pixelPtr <= "00000000000000000000";
+
+ rpi_position <= '0' & x"0000";
+ HFragments <= x"11";
+ VFragments <= x"00";
+ YStride <= x"000";
+ UVStride <= "000" & x"00";
+ YPlaneFragments <= '0' & x"00000";
+ UVPlaneFragments <= "000" & x"0000";
+ ReconYDataOffset <= x"00000";
+ ReconUDataOffset <= x"00000";
+ ReconVDataOffset <= x"00000";
+
+-- FLimits signals initialiation
+ fbv_position <= "000000000";
+ FLimit <= "000000000";
+
+
+-- QThreshTable signal memories
+ qtt_wr_e <= '0';
+ qtt_wr_addr <= "000000";
+ qtt_wr_data <= "00000000000000000000000000000000";
+ qtt_rd_addr <= "000000";
+
+
+--display_fragments signal memories
+ dpf_wr_e <= '0';
+ dpf_wr_addr <= to_unsigned(0, DPF_ADDR_WIDTH);
+ dpf_wr_data <= "00000000000000000000000000000000";
+ dpf_rd_addr <= to_unsigned(0, DPF_ADDR_WIDTH);
+ else
+ if (Enable = '1') then
+ case state is
+ when readIn => ReadIn;
+ when proc => Proc;
+ when others => ReadIn; state <= readIn;
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+
+
+end a_LoopFilter;
Property changes on: trunk/theora-fpga/theora_hardware/loopfilter.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/reconframes.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/reconframes.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/reconframes.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,335 @@
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+entity ReconFrames is
+ port (
+ Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic;
+ out_eb_done : out std_logic);
+end ReconFrames;
+
+architecture a_ReconFrames of ReconFrames is
+ component ExpandBlock
+ port (
+ Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ in_newframe : in std_logic;
+ out_done : out std_logic);
+ end component;
+
+ constant LG_MAX_SIZE : natural := 10;
+ constant MEM_ADDR_WIDTH : natural := 20;
+-------------------------------------------------------------------------------
+-- ExpandBlock's signals
+-------------------------------------------------------------------------------
+ signal out_eb_request : std_logic;
+ signal out_eb_valid : std_logic := '0';
+ signal out_eb_data : signed(31 downto 0);
+
+ signal in_eb_DtBuf_request : std_logic;
+ signal in_eb_DtBuf_valid : std_logic;
+ signal in_eb_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal in_eb_DtBuf_data : signed(31 downto 0);
+
+ signal out_eb_DtBuf_request : std_logic;
+ signal out_eb_DtBuf_valid : std_logic;
+ signal out_eb_DtBuf_addr : unsigned(19 downto 0);
+ signal out_eb_DtBuf_data : signed(31 downto 0);
+
+ signal eb_done : std_logic;
+ signal eb_enable : std_logic;
+
+-------------------------------------------------------------------------------
+-- Internal signals
+-------------------------------------------------------------------------------
+ signal QuantDispFrags : unsigned(LG_MAX_SIZE*2-1 downto 0);
+
+ signal count : integer;
+ signal countExpand : unsigned(LG_MAX_SIZE*2-1 downto 0);
+ signal s_in_request : std_logic;
+
+ signal s_out_done : std_logic;
+-------------------------------------------------------------------------------
+-- States and sub-states
+-------------------------------------------------------------------------------
+ type state_t is (stt_Read, stt_Proc);
+ signal state : state_t;
+
+ type read_state_t is (stt_read_HFragments,
+ stt_read_YPlaneFragments,
+ stt_read_YStride,
+ stt_read_UVPlaneFragments,
+ stt_read_UVStride,
+ stt_read_VFragments,
+ stt_read_ReconYDataOffset,
+ stt_read_ReconUDataOffset,
+ stt_read_ReconVDataOffset,
+ stt_read_QuantDispFrags,
+ stt_read_Others);
+ signal read_state : read_state_t;
+
+begin -- a_ReconFrames
+
+ expandblock0: expandblock
+ port map(
+ Clk => clk,
+ Reset_n => reset_n,
+ Enable => eb_enable,
+
+ in_request => out_eb_request,
+ in_valid => out_eb_valid,
+ in_data => out_eb_data,
+
+ in_sem_request => out_eb_DtBuf_request,
+ in_sem_valid => out_eb_DtBuf_valid,
+ in_sem_addr => out_eb_DtBuf_addr,
+ in_sem_data => out_eb_DtBuf_data,
+
+ out_sem_requested => in_eb_DtBuf_request,
+ out_sem_valid => in_eb_DtBuf_valid,
+ out_sem_addr => in_eb_DtBuf_addr,
+ out_sem_data => in_eb_DtBuf_data,
+
+ in_newframe => s_out_done,
+ out_done => eb_done
+ );
+
+ in_sem_request <= out_eb_DtBuf_request;
+ out_eb_DtBuf_valid <= in_sem_valid;
+ in_sem_addr <= out_eb_DtBuf_addr;
+ out_eb_DtBuf_data <= in_sem_data;
+
+ in_eb_DtBuf_request <= out_sem_requested;
+ out_sem_valid <= in_eb_DtBuf_valid;
+ out_sem_addr <= in_eb_DtBuf_addr;
+ out_sem_data <= in_eb_DtBuf_data;
+ out_eb_data <= in_data;
+ in_request <= s_in_request;
+
+
+ -----------------------------------------------------------------------------
+ -- Put the s_out_done signal on the output port
+ -----------------------------------------------------------------------------
+ out_done <= s_out_done;
+
+ -----------------------------------------------------------------------------
+ -- Switch the in_request
+ -----------------------------------------------------------------------------
+ process(read_state, out_eb_request, in_valid, Enable)
+ begin
+ s_in_request <= out_eb_request;
+ out_eb_valid <= in_valid;
+ if (read_state = stt_read_QuantDispFrags) then
+ s_in_request <= '1';
+ out_eb_valid <= '0';
+ end if;
+ if (Enable = '0') then
+ s_in_request <= '0';
+ out_eb_valid <= '0';
+ end if;
+ end process;
+
+
+ process(clk)
+ variable QuantDispFragsIsZero : std_logic;
+ begin
+
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ s_out_done <= '0';
+ count <= 0;
+ countExpand <= to_unsigned(0, LG_MAX_SIZE*2);
+ eb_enable <= '1';
+ QuantDispFrags <= to_unsigned(0, LG_MAX_SIZE*2);
+ read_state <= stt_read_HFragments;
+ else
+ s_out_done <= '0';
+ out_eb_done <= '0';
+ if (Enable = '1') then
+ case state is
+
+ when stt_Read =>
+
+-- assert false report "read_state = "&read_state_t'image(read_state) severity note;
+
+ if (s_in_request = '1' and in_valid = '1') then
+-- assert false report "rf.in_data = "&integer'image(to_integer(in_data)) severity note;
+ count <= count + 1;
+ case read_state is
+ when stt_read_HFragments =>
+ -- Count = 0
+ read_state <= stt_read_YPlaneFragments;
+
+ when stt_read_YPlaneFragments =>
+ -- Count = 1
+ read_state <= stt_read_YStride;
+
+ when stt_read_YStride =>
+ -- Count = 2
+ read_state <= stt_read_UVPlaneFragments;
+
+ when stt_read_UVPlaneFragments =>
+ -- Count = 3
+ read_state <= stt_read_UVStride;
+
+ when stt_read_UVStride =>
+ -- Count = 4
+ read_state <= stt_read_VFragments;
+
+ when stt_read_VFragments =>
+ -- Count = 5
+ read_state <= stt_read_ReconYDataOffset;
+
+ when stt_read_ReconYDataOffset =>
+ -- Count = 6
+ read_state <= stt_read_ReconUDataOffset;
+
+ when stt_read_ReconUDataOffset =>
+ -- Count = 7
+ read_state <= stt_read_ReconVDataOffset;
+
+ when stt_read_ReconVDataOffset =>
+ -- Count = 8
+ read_state <= stt_read_QuantDispFrags;
+
+ when stt_read_QuantDispFrags =>
+ -- Count = 9
+ -- One per Frame
+ -- QuantDispFrags is equal to pbi->CodedBlockIndex of the software
+ read_state <= stt_read_Others;
+ QuantDispFrags <= unsigned(in_data(LG_MAX_SIZE*2-1 downto 0));
+ if (in_data(LG_MAX_SIZE*2-1 downto 0) = 0) then
+ state <= stt_Proc;
+ end if;
+ when others =>
+ -----------------------------------------------------------
+ -- Forward to ExpandBlock the parameters below that are
+ -- received only one time pre frame
+ -----------------------------------------------------------
+ -- For Count = 10 to Count = 73 receive the
+ -- pbi->dequant_Y_coeffs matrix
+ -----------------------------------------------------------
+ -- For Count = 74 to Count = 137 receive the
+ -- pbi->dequant_U_coeffs matrix
+ -----------------------------------------------------------
+ -- For Count = 138 to Count = 201 receive the
+ -- pbi->dequant_V_coeffs matrix
+ -----------------------------------------------------------
+ -- For Count = 202 to Count = 265 receive the
+ -- dequant_InterY_coeffs matrix
+ -----------------------------------------------------------
+ -- For Count = 266 to Count = 329 receive the
+ -- dequant_InterU_coeffs matrix
+ -----------------------------------------------------------
+ -- For Count = 330 to Count = 393 receive the
+ -- dequant_InterV_coeffs matrix
+ -----------------------------------------------------------
+ -- If Count = 394 receive the pbi->FrameType value
+ -----------------------------------------------------------
+ -- If Count = 395 receive the
+ -- Offset of the GoldenFrame Buffer
+ -----------------------------------------------------------
+ -- If Count = 396 receive the
+ -- Offset of the LastFrame Buffer
+ -----------------------------------------------------------
+ -- If Count = 397 receive the
+ -- Offset of the ThisFrame Buffer
+ -----------------------------------------------------------
+
+ -----------------------------------------------------------
+ -- Forward to ExpandBlock the parameters below that are
+ -- received for all fragments
+ -----------------------------------------------------------
+ -- For Count = 398 to Count = 461 receive the
+ -- pbi->QFragData(number of the fragment to be expanded)
+ -- matrix
+ ------------------------------------------------------------
+ -- If Count = 462 receive the
+ -- pbi->FragCodingMethod(number of the fragment to be expanded)
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 463 receive the
+ -- pbi->FragCoefEOB(number of the fragment to be expanded)
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 464 receive the
+ -- (pbi->FragMVect(number of the fragment to be expanded)).x
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 465 receive the
+ -- (pbi->FragMVect(number of the fragment to be expanded)).y
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 466 receive the
+ -- (number of fragment to be expanded)
+ -----------------------------------------------------------
+ if (count = 466) then
+ state <= stt_Proc;
+ count <= 398;
+ end if;
+ end case;
+ end if;
+
+ when stt_Proc =>
+ if (QuantDispFrags = 0) then
+ QuantDispFragsIsZero := '1';
+ else
+ QuantDispFragsIsZero := '0';
+ end if;
+
+ if (eb_done = '1' or QuantDispFragsIsZero = '1') then
+ out_eb_done <= '1';
+ countExpand <= countExpand + 1;
+ state <= stt_Read;
+ if (countExpand = TO_INTEGER(QuantDispFrags-1) or QuantDispFragsIsZero = '1') then
+ count <= 9;
+ read_state <= stt_read_QuantDispFrags;
+ countExpand <= to_unsigned(0, LG_MAX_SIZE*2);
+ s_out_done <= '1';
+ end if;
+ end if;
+
+ end case;
+ end if;
+ end if;
+ end if;
+ end process;
+end a_ReconFrames;
Property changes on: trunk/theora-fpga/theora_hardware/reconframes.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/reconpixelindex.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/reconpixelindex.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/reconpixelindex.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,256 @@
+library std;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ReconPixelIndex is
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+end entity ReconPixelIndex;
+
+architecture a_ReconPixelIndex of ReconPixelIndex is
+ component Divider
+ generic (
+ WIDTH : positive := 32);
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ dividend : in unsigned(WIDTH-1 downto 0);
+ divisor : in unsigned(WIDTH-1 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ quotient : out unsigned(WIDTH-1 downto 0);
+ remainder : out unsigned(WIDTH-1 downto 0));
+ end component;
+
+
+
+ constant VFRAGPIXELS : unsigned(3 downto 0) := x"8";
+ constant HFRAGPIXELS : unsigned(3 downto 0) := x"8";
+
+ constant RPI_POS_WIDTH : positive := 17;
+ constant HV_FRAG_WIDTH : positive := 8;
+ constant Y_STRIDE_WIDTH : positive := 12;
+ constant UV_STRIDE_WIDTH : positive := 11;
+ constant Y_PL_FRAG_WIDTH : positive := 21;
+ constant UV_PL_FRAG_WIDTH : positive := 19;
+ constant RECON_Y_DATA_OFS_WIDTH : positive := 20;
+ constant RECON_UV_DATA_OFS_WIDTH : positive := 20;
+
+ -- States machines
+ type state_t is (stt_readIn, stt_Proc, stt_WriteOut);
+ signal state : state_t;
+
+ type read_state_t is (stt_read_HFragments,
+ stt_read_YPlaneFragments,
+ stt_read_YStride,
+ stt_read_UVPlaneFragments,
+ stt_read_UVStride,
+ stt_read_VFragments,
+ stt_read_ReconYDataOffset,
+ stt_read_ReconUDataOffset,
+ stt_read_ReconVDataOffset,
+ stt_read_Position);
+ signal read_state : read_state_t;
+
+ type proc_state_t is (stt_proc_1, stt_proc_2);
+ signal proc_state : proc_state_t;
+
+ -- Signals that will be received
+ signal rpi_position : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal HFragments : unsigned(HV_FRAG_WIDTH-1 downto 0);
+-- signal VFragments : unsigned(HV_FRAG_WIDTH-1 downto 0);
+ signal YStride : unsigned(Y_STRIDE_WIDTH-1 downto 0);
+ signal UVStride : unsigned(UV_STRIDE_WIDTH-1 downto 0);
+ signal YPlaneFragments : unsigned(Y_PL_FRAG_WIDTH-1 downto 0);
+ signal UVPlaneFragments : unsigned(UV_PL_FRAG_WIDTH-1 downto 0);
+ signal ReconYDataOffset : unsigned(RECON_Y_DATA_OFS_WIDTH-1 downto 0);
+ signal ReconUDataOffset : unsigned(RECON_UV_DATA_OFS_WIDTH-1 downto 0);
+ signal ReconVDataOffset : unsigned(RECON_UV_DATA_OFS_WIDTH-1 downto 0);
+
+ -- Calculated value
+ signal rpi_value : signed(31 downto 0);
+
+ -- Handshake signals
+ signal s_in_request : std_logic;
+ signal s_out_valid : std_logic;
+
+ -- Divider signals
+ signal s_divider_in_request : std_logic;
+ signal s_divider_in_valid : std_logic;
+ signal s_divider_dividend : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal s_divider_divisor : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal s_divider_out_requested : std_logic;
+ signal s_divider_out_valid : std_logic;
+ signal s_divider_quotient : unsigned(RPI_POS_WIDTH-1 downto 0);
+ signal s_divider_remainder : unsigned(RPI_POS_WIDTH-1 downto 0);
+
+
+begin -- a_ReconPixelIndex
+
+ divider0: divider
+ generic map (WIDTH => RPI_POS_WIDTH)
+ port map(Clk => Clk,
+ Reset_n => Reset_n,
+ in_request => s_divider_out_requested,
+ in_valid => s_divider_out_valid,
+ dividend => s_divider_dividend,
+ divisor => s_divider_divisor,
+ out_requested => s_divider_in_request,
+ out_valid => s_divider_in_valid,
+ quotient => s_divider_quotient,
+ remainder => s_divider_remainder);
+
+ in_request <= s_in_request;
+ out_valid <= s_out_valid;
+ process(clk)
+
+ procedure ReadIn is
+ begin
+ s_in_request <= '1';
+ s_out_valid <= '0';
+
+ if (s_in_request = '1' and in_valid = '1') then
+
+ case read_state is
+ when stt_read_HFragments =>
+ read_state <= stt_read_YPlaneFragments;
+ HFragments <= unsigned(in_data(HV_FRAG_WIDTH-1 downto 0));
+
+ when stt_read_YPlaneFragments =>
+ read_state <= stt_read_YStride;
+ YPlaneFragments <= unsigned(in_data(Y_PL_FRAG_WIDTH-1 downto 0));
+
+ when stt_read_YStride =>
+ read_state <= stt_read_UVPlaneFragments;
+ YStride <= unsigned(in_data(Y_STRIDE_WIDTH-1 downto 0));
+
+ when stt_read_UVPlaneFragments =>
+ read_state <= stt_read_UVStride;
+ UVPlaneFragments <= unsigned(in_data(UV_PL_FRAG_WIDTH-1 downto 0));
+
+ when stt_read_UVStride =>
+ read_state <= stt_read_VFragments;
+ UVStride <= unsigned(in_data(UV_STRIDE_WIDTH-1 downto 0));
+
+ when stt_read_VFragments =>
+ read_state <= stt_read_ReconYDataOffset;
+-- VFragments <= unsigned(in_data(HV_FRAG_WIDTH-1 downto 0));
+
+ when stt_read_ReconYDataOffset =>
+ read_state <= stt_read_ReconUDataOffset;
+ ReconYDataOffset <= unsigned(in_data(RECON_Y_DATA_OFS_WIDTH-1 downto 0));
+
+ when stt_read_ReconUDataOffset =>
+ read_state <= stt_read_ReconVDataOffset;
+ ReconUDataOffset <= unsigned(in_data(RECON_UV_DATA_OFS_WIDTH-1 downto 0));
+
+ when stt_read_ReconVDataOffset =>
+ read_state <= stt_read_Position;
+ ReconVDataOffset <= unsigned(in_data(RECON_UV_DATA_OFS_WIDTH-1 downto 0));
+
+ when others => -- stt_read_Position
+ read_state <= stt_read_Position;
+ state <= stt_Proc;
+ proc_state <= stt_proc_1;
+ rpi_position <= unsigned(in_data(RPI_POS_WIDTH-1 downto 0));
+ s_in_request <= '0';
+ end case;
+ end if;
+ end procedure ReadIn;
+
+ procedure Proc is
+ begin
+ s_divider_out_valid <= '0';
+ s_divider_in_request <= '0';
+ case proc_state is
+ when stt_proc_1 =>
+ if (s_divider_out_requested = '1') then
+ s_divider_out_valid <= '1';
+ s_divider_in_request <= '1';
+ proc_state <= stt_proc_2;
+ if (rpi_position < YPlaneFragments) then
+ s_divider_dividend <= rpi_position;
+ s_divider_divisor <= resize(HFragments, RPI_POS_WIDTH);
+ rpi_value <= resize(signed('0' & ReconYDataOffset), 32);
+
+ elsif (rpi_position < YPlaneFragments + UVPlaneFragments) then
+ s_divider_dividend <= resize(rpi_position - YPlaneFragments, RPI_POS_WIDTH);
+ s_divider_divisor <= resize(SHIFT_RIGHT(HFragments, 1), RPI_POS_WIDTH);
+ rpi_value <= resize(signed('0' & ReconUDataOffset) , 32);
+ else
+ s_divider_dividend <= resize(rpi_position - (YPlaneFragments + UVPlaneFragments), RPI_POS_WIDTH);
+ s_divider_divisor <= resize(SHIFT_RIGHT(HFragments, 1), RPI_POS_WIDTH);
+ rpi_value <= resize(signed('0' & ReconVDataOffset), 32);
+ end if;
+ end if;
+
+
+
+ when others =>
+ s_divider_in_request <= '1';
+ if (s_divider_in_request = '1' and s_divider_in_valid = '1') then
+ s_divider_in_request <= '0';
+ proc_state <= stt_proc_1;
+ state <= stt_WriteOut;
+
+ if (rpi_position < YPlaneFragments) then
+ rpi_value <= rpi_value +
+ resize(signed('0' &
+ (s_divider_quotient * VFRAGPIXELS * YStride +
+ s_divider_remainder * HFRAGPIXELS)), 32);
+ else
+ rpi_value <= rpi_value +
+ resize(signed('0' &
+ (s_divider_quotient * VFRAGPIXELS * UVStride +
+ s_divider_remainder * HFRAGPIXELS)), 32);
+
+ end if;
+
+ end if;
+ end case;
+ end procedure Proc;
+
+ procedure WriteOut is
+ begin
+ s_out_valid <= '1';
+ out_data <= rpi_value;
+ if (out_requested = '1') then
+ state <= stt_readIn;
+ end if;
+ end procedure WriteOut;
+
+
+
+ begin
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ state <= stt_readIn;
+ read_state <= stt_read_HFragments;
+ proc_state <= stt_proc_1;
+ s_in_request <= '0';
+ s_out_valid <= '0';
+ else
+ case state is
+ when stt_readIn => ReadIn;
+ when stt_Proc => Proc;
+ when others => WriteOut;
+ end case;
+ end if;
+ end if;
+
+ end process;
+
+end a_ReconPixelIndex;
Property changes on: trunk/theora-fpga/theora_hardware/reconpixelindex.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/reconrefframes.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/reconrefframes.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/reconrefframes.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,1158 @@
+library std;
+library ieee;
+library work;
+
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use work.all;
+
+
+entity ReconRefFrames is
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+end entity ReconRefFrames;
+
+architecture a_ReconRefFrames of ReconRefFrames is
+ component ReconFrames
+ port (
+ Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic;
+ out_eb_done : out std_logic);
+ end component;
+
+
+ component LoopFilter
+ port (Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic
+ );
+ end component;
+
+ component CopyRecon
+ port (Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic
+ );
+ end component;
+
+
+ component UpdateUMV
+ port (Clk,
+ Reset_n : in std_logic;
+ Enable : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ in_sem_request : out std_logic;
+ in_sem_valid : in std_logic;
+ in_sem_addr : out unsigned(19 downto 0);
+ in_sem_data : in signed(31 downto 0);
+
+ out_sem_requested : in std_logic;
+ out_sem_valid : out std_logic;
+ out_sem_addr : out unsigned(19 downto 0);
+ out_sem_data : out signed(31 downto 0);
+
+ out_done : out std_logic
+ );
+ end component;
+
+ component DataBuffer
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_addr : in unsigned(19 downto 0);
+ in_data : in signed(31 downto 0);
+
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_addr : in unsigned(19 downto 0);
+ out_data : out signed(31 downto 0)
+ );
+ end component;
+
+ constant LG_MAX_SIZE : natural := 10;
+ constant MEM_ADDR_WIDTH : natural := 20;
+-------------------------------------------------------------------------------
+-- Buffer's signals
+-------------------------------------------------------------------------------
+ signal in_DtBuf_request : std_logic;
+ signal in_DtBuf_valid : std_logic;
+ signal in_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal in_DtBuf_data : signed(31 downto 0);
+
+ signal out_DtBuf_request : std_logic;
+ signal out_DtBuf_valid : std_logic;
+ signal out_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal out_DtBuf_data : signed(31 downto 0);
+
+-------------------------------------------------------------------------------
+-- ReconFrames' signals
+-------------------------------------------------------------------------------
+ signal out_rf_request : std_logic;
+ signal out_rf_valid : std_logic := '0';
+ signal out_rf_data : signed(31 downto 0);
+
+ signal in_rf_DtBuf_request : std_logic;
+ signal in_rf_DtBuf_valid : std_logic;
+ signal in_rf_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal in_rf_DtBuf_data : signed(31 downto 0);
+
+ signal out_rf_DtBuf_request : std_logic;
+ signal out_rf_DtBuf_valid : std_logic;
+ signal out_rf_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal out_rf_DtBuf_data : signed(31 downto 0);
+
+ signal rf_done : std_logic;
+ signal rf_eb_done : std_logic;
+ signal rf_enable : std_logic;
+
+-------------------------------------------------------------------------------
+-- CopyRecon's signals
+-------------------------------------------------------------------------------
+ signal out_cr_request : std_logic;
+ signal out_cr_valid : std_logic := '0';
+ signal out_cr_data : signed(31 downto 0);
+
+ signal in_cr_DtBuf_request : std_logic;
+ signal in_cr_DtBuf_valid : std_logic;
+ signal in_cr_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal in_cr_DtBuf_data : signed(31 downto 0);
+
+ signal out_cr_DtBuf_request : std_logic;
+ signal out_cr_DtBuf_valid : std_logic;
+ signal out_cr_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal out_cr_DtBuf_data : signed(31 downto 0);
+
+ signal cr_done : std_logic;
+ signal cr_enable : std_logic;
+
+-------------------------------------------------------------------------------
+-- LoopFilter's signals
+-------------------------------------------------------------------------------
+ signal out_lf_request : std_logic;
+ signal out_lf_valid : std_logic := '0';
+ signal out_lf_data : signed(31 downto 0);
+
+ signal in_lf_DtBuf_request : std_logic;
+ signal in_lf_DtBuf_valid : std_logic;
+ signal in_lf_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal in_lf_DtBuf_data : signed(31 downto 0);
+
+ signal out_lf_DtBuf_request : std_logic;
+ signal out_lf_DtBuf_valid : std_logic;
+ signal out_lf_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal out_lf_DtBuf_data : signed(31 downto 0);
+
+ signal lf_done : std_logic;
+ signal lf_enable : std_logic;
+
+-------------------------------------------------------------------------------
+-- UpdateUMV's signals
+-------------------------------------------------------------------------------
+ signal out_uu_request : std_logic;
+ signal out_uu_valid : std_logic := '0';
+ signal out_uu_data : signed(31 downto 0);
+
+ signal in_uu_DtBuf_request : std_logic;
+ signal in_uu_DtBuf_valid : std_logic;
+ signal in_uu_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal in_uu_DtBuf_data : signed(31 downto 0);
+
+ signal out_uu_DtBuf_request : std_logic;
+ signal out_uu_DtBuf_valid : std_logic;
+ signal out_uu_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal out_uu_DtBuf_data : signed(31 downto 0);
+
+ signal uu_done : std_logic;
+ signal uu_enable : std_logic;
+
+-------------------------------------------------------------------------------
+ signal in_rr_DtBuf_request : std_logic;
+ signal in_rr_DtBuf_valid : std_logic;
+ signal in_rr_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+ signal out_rr_DtBuf_request : std_logic;
+ signal out_rr_DtBuf_valid : std_logic;
+ signal out_rr_DtBuf_addr : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal out_rr_DtBuf_data : signed(31 downto 0);
+
+
+ signal FrameSize : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal GoldenFrameOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ThisFrameReconOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal LastFrameReconOfs : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+ signal FrameOfsAux : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal FrameOfsAuxSrc : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+
+ signal FrameType : unsigned(7 downto 0);
+ signal MaxDPFCount : unsigned(LG_MAX_SIZE*2 downto 0);
+
+ signal s_in_request : std_logic;
+ signal s_in_valid : std_logic;
+
+ signal CountCopies : std_logic;
+ signal CountUpdates : std_logic;
+ signal count : integer range 0 to 2097151;
+
+ signal count_lines : integer range 0 to 1023;
+ signal count_columns : integer range 0 to 1023;
+
+ constant KEY_FRAME : unsigned(7 downto 0) := "00000000";
+
+ type state_t is (stt_CleanBuffer,
+ stt_Forward, stt_ReconFrames,
+ stt_CopyRecon, stt_LoopFilter,
+ stt_UpdateUMV, stt_WriteOut);
+ signal state : state_t;
+
+
+ type forward_state_t is (stt_rec_framesize,
+ stt_rec_height,
+ stt_rec_width,
+ stt_forward_uniq_common,
+ stt_forward_uniq_cr_lf,
+ stt_forward_uniq_lf,
+ stt_forward_uniq_uu,
+ stt_forward_uniqperframe_rf,
+ stt_frametype,
+ stt_forward_golden_ofs_rf,
+ stt_forward_last_ofs_rf,
+ stt_forward_this_ofs_rf,
+ stt_forward_rf,
+ stt_forward_dispfrag,
+ stt_forward_source_ofs_cr,
+ stt_forward_dest_ofs_cr,
+ stt_forward_lf,
+ stt_forward_offset_lf,
+ stt_forward_offset_uu,
+ stt_forward_dispfrag_golden,
+ stt_forward_none);
+ signal forward_state : forward_state_t;
+
+ type write_state_t is (stt_write1, stt_write2, stt_write3);
+ signal write_state : write_state_t;
+
+ type plane_write_state_t is (stt_plane_write_Y, stt_plane_write_Cb, stt_plane_write_Cr);
+ signal plane_write_state : plane_write_state_t;
+
+-- Fragment Parameters
+ signal YStride : unsigned(LG_MAX_SIZE+1 downto 0);
+ signal UVStride : unsigned(LG_MAX_SIZE downto 0);
+ signal ReconYDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconUDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal ReconVDataOffset : unsigned(MEM_ADDR_WIDTH-1 downto 0);
+ signal video_height : unsigned(9 downto 0);
+ signal video_width : unsigned(9 downto 0);
+
+ signal s_out_valid : std_logic;
+ signal s_out_data : signed(31 downto 0);
+
+
+-- signal count_leo : integer range 0 to 127 := 0;
+
+begin -- a_ReconRefFrames
+
+ reconframes0: reconframes
+ port map(clk, Reset_n, rf_enable,
+ out_rf_request, out_rf_valid, out_rf_data,
+ out_rf_DtBuf_request, out_rf_DtBuf_valid, out_rf_DtBuf_addr, out_rf_DtBuf_data,
+ in_rf_DtBuf_request, in_rf_DtBuf_valid, in_rf_DtBuf_addr, in_rf_DtBuf_data,
+ rf_done, rf_eb_done);
+
+ loopfilter0: loopfilter
+ port map(clk, Reset_n, rf_enable,
+ out_lf_request, out_lf_valid, out_lf_data,
+ out_lf_DtBuf_request, out_lf_DtBuf_valid, out_lf_DtBuf_addr, out_lf_DtBuf_data,
+ in_lf_DtBuf_request, in_lf_DtBuf_valid, in_lf_DtBuf_addr, in_lf_DtBuf_data,
+ lf_done);
+
+ copyrecon0: copyrecon
+ port map(clk, Reset_n, cr_enable,
+ out_cr_request, out_cr_valid, out_cr_data,
+ out_cr_DtBuf_request, out_cr_DtBuf_valid, out_cr_DtBuf_addr, out_cr_DtBuf_data,
+ in_cr_DtBuf_request, in_cr_DtBuf_valid, in_cr_DtBuf_addr, in_cr_DtBuf_data,
+ cr_done);
+
+ updateumv0: UpdateUMV
+ port map(clk, Reset_n, uu_enable,
+ out_uu_request, out_uu_valid, out_uu_data,
+ out_uu_DtBuf_request, out_uu_DtBuf_valid, out_uu_DtBuf_addr, out_uu_DtBuf_data,
+ in_uu_DtBuf_request, in_uu_DtBuf_valid, in_uu_DtBuf_addr, in_uu_DtBuf_data,
+ uu_done);
+
+ databuffer0: databuffer
+ port map(clk, Reset_n,
+ out_DtBuf_request, out_DtBuf_valid, out_DtBuf_addr, out_DtBuf_data,
+ in_DtBuf_request, in_DtBuf_valid, in_DtBuf_addr, in_DtBuf_data);
+
+
+ out_valid <= s_out_valid;
+ -----------------------------------------------------------------------------
+ -- Switch the in_request
+ -----------------------------------------------------------------------------
+ -- If forward_state is a state that doesn't need external data then
+ -- in_request will be turned off
+ with forward_state select in_request <=
+ '0' when stt_forward_golden_ofs_rf,
+ '0' when stt_forward_last_ofs_rf,
+ '0' when stt_forward_this_ofs_rf,
+ '0' when stt_forward_source_ofs_cr,
+ '0' when stt_forward_dest_ofs_cr,
+ '0' when stt_forward_offset_lf,
+ '0' when stt_forward_offset_uu,
+ '0' when stt_forward_dispfrag_golden,
+ '0' when stt_forward_none,
+ s_in_request when others;
+
+ -----------------------------------------------------------------------------
+ -- Switch the signals of the in_data and in_valid of the modules
+ -----------------------------------------------------------------------------
+ process (Reset_n,
+ forward_state,
+ out_rf_request,
+ out_cr_request,
+ out_lf_request,
+ out_uu_request,
+ in_valid,
+ in_data,
+ GoldenFrameOfs,
+ LastFrameReconOfs,
+ ThisFrameReconOfs,
+ FrameOfsAuxSrc,
+ FrameOfsAux)
+
+ begin
+
+ out_rf_valid <= '0';
+ out_rf_data <= in_data;
+ out_cr_valid <= '0';
+ out_cr_data <= in_data;
+ out_lf_valid <= '0';
+ out_lf_data <= in_data;
+ out_uu_valid <= '0';
+ out_uu_data <= in_data;
+
+ s_in_valid <= in_valid;
+ s_in_request <= '0';
+
+ -----------------------------------------------------------------------------
+ -- Unique Parameters
+ -----------------------------------------------------------------------------
+ if (forward_state = stt_rec_framesize) then
+ s_in_request <= '1';
+
+ elsif (forward_state = stt_rec_height) then
+ s_in_request <= '1';
+
+ elsif (forward_state = stt_rec_width) then
+ s_in_request <= '1';
+
+ elsif (forward_state = stt_forward_uniq_common) then
+ s_in_request <= out_rf_request and
+ out_cr_request and
+ out_lf_request and
+ out_uu_request;
+ out_rf_valid <= in_valid;
+ out_cr_valid <= in_valid;
+ out_lf_valid <= in_valid;
+ out_uu_valid <= in_valid;
+
+ elsif (forward_state = stt_forward_uniq_cr_lf) then
+ -------------------------------------------------------------------------
+ -- UnitFragment is sent to CopyRecon and LoopFilter and read internaly
+ -------------------------------------------------------------------------
+ s_in_request <= out_cr_request and
+ out_lf_request;
+
+ out_cr_valid <= in_valid;
+ out_lf_valid <= in_valid;
+
+ elsif (forward_state = stt_forward_uniq_lf) then
+ s_in_request <= out_lf_request;
+ out_lf_valid <= in_valid;
+
+ elsif (forward_state = stt_forward_uniq_uu) then
+ s_in_request <= out_uu_request;
+ out_uu_valid <= in_valid;
+
+
+ -----------------------------------------------------------------------
+ -- ReconFrames Parameters
+ ---------------------------------------------------------------------------
+ elsif (forward_state = stt_forward_uniqperframe_rf) then
+ s_in_request <= out_rf_request;
+ out_rf_valid <= in_valid;
+
+ elsif (forward_state = stt_frametype) then
+ -------------------------------------------------------------------------
+ -- FrameType is sent to ReconFrames and read internaly
+ -------------------------------------------------------------------------
+ s_in_request <= out_rf_request;
+ out_rf_valid <= in_valid;
+
+ elsif (forward_state = stt_forward_golden_ofs_rf) then
+ s_in_request <= out_rf_request;
+ s_in_valid <= '1';
+ out_rf_valid <= '1';
+ out_rf_data <= resize('0' & signed(GoldenFrameOfs), 32);
+
+ elsif (forward_state = stt_forward_last_ofs_rf) then
+ s_in_request <= out_rf_request;
+ s_in_valid <= '1';
+ out_rf_valid <= '1';
+ out_rf_data <= resize('0' & signed(LastFrameReconOfs), 32);
+
+ elsif (forward_state = stt_forward_this_ofs_rf) then
+ s_in_request <= out_rf_request;
+ s_in_valid <= '1';
+ out_rf_valid <= '1';
+ out_rf_data <= resize('0' & signed(ThisFrameReconOfs), 32);
+
+ elsif (forward_state = stt_forward_rf) then
+ s_in_request <= out_rf_request;
+ out_rf_valid <= in_valid;
+
+ elsif (forward_state = stt_forward_dispfrag) then
+ s_in_request <= out_cr_request and
+ out_lf_request;
+ out_cr_valid <= '0';
+ out_lf_valid <= '0';
+ if ((out_cr_request and out_lf_request)= '1') then
+ out_cr_valid <= in_valid;
+ out_lf_valid <= in_valid;
+ else
+ assert false report "Somebody doesn't want read" severity note;
+ end if;
+
+ elsif (forward_state = stt_forward_source_ofs_cr) then
+ s_in_request <= out_cr_request;
+ s_in_valid <= '1';
+ out_cr_valid <= '1';
+ out_cr_data <= resize('0' & signed(FrameOfsAuxSrc), 32);
+
+ elsif (forward_state = stt_forward_dest_ofs_cr) then
+ s_in_request <= out_cr_request;
+ s_in_valid <= '1';
+ out_cr_valid <= '1';
+ out_cr_data <= resize('0' & signed(FrameOfsAux), 32);
+
+ elsif (forward_state = stt_forward_lf) then
+ s_in_request <= out_lf_request;
+ out_lf_valid <= in_valid;
+
+ elsif (forward_state = stt_forward_offset_lf) then
+ s_in_request <= out_lf_request;
+ s_in_valid <= '1';
+ out_lf_valid <= '1';
+ out_lf_data <= resize('0' & signed(LastFrameReconOfs), 32);
+
+ elsif (forward_state = stt_forward_offset_uu) then
+ s_in_request <= out_uu_request;
+ s_in_valid <= '1';
+ out_uu_valid <= '1';
+ out_uu_data <= resize('0' & signed(FrameOfsAux), 32);
+
+ elsif (forward_state = stt_forward_dispfrag_golden) then
+ -------------------------------------------------------------------------
+ -- If it is a key frame then all fragments must be displayed.
+ -- In such case all values of display_fragments is one
+ -------------------------------------------------------------------------
+ s_in_request <= out_cr_request;
+ s_in_valid <= '1';
+ out_cr_valid <= '1';
+ out_cr_data <= x"FFFFFFFF";
+ else
+ null;
+ end if;
+ if (Reset_n = '0') then
+ out_rf_valid <= '0';
+ out_cr_valid <= '0';
+ out_lf_valid <= '0';
+ out_uu_valid <= '0';
+ s_in_request <= '0';
+ end if;
+ end process;
+
+ -----------------------------------------------------------------------------
+ -- Control the module's access to the Data Buffer
+ -- This is just a big multiplexer
+ -----------------------------------------------------------------------------
+ process (Reset_n,
+ state,
+ in_DtBuf_valid,
+ in_DtBuf_data,
+ out_DtBuf_request,
+
+ out_rf_DtBuf_request,
+ out_rf_DtBuf_addr,
+ in_rf_DtBuf_valid,
+ in_rf_DtBuf_addr,
+ in_rf_DtBuf_data,
+
+ out_cr_DtBuf_request,
+ out_cr_DtBuf_addr,
+ in_cr_DtBuf_valid,
+ in_cr_DtBuf_addr,
+ in_cr_DtBuf_data,
+
+ out_lf_DtBuf_request,
+ out_lf_DtBuf_addr,
+ in_lf_DtBuf_valid,
+ in_lf_DtBuf_addr,
+ in_lf_DtBuf_data,
+
+ out_uu_DtBuf_request,
+ out_uu_DtBuf_addr,
+ in_uu_DtBuf_valid,
+ in_uu_DtBuf_addr,
+ in_uu_DtBuf_data,
+
+ out_rr_DtBuf_request,
+ out_rr_DtBuf_addr,
+ in_rr_DtBuf_valid,
+ in_rr_DtBuf_addr
+ )
+ begin -- process state
+ out_rr_DtBuf_data <= x"00000000";
+ out_rr_DtBuf_valid <= '0';
+
+ out_cr_DtBuf_data <= x"00000000";
+ out_cr_DtBuf_valid <= '0';
+
+ out_lf_DtBuf_data <= x"00000000";
+ out_lf_DtBuf_valid <= '0';
+
+ out_rf_DtBuf_data <= x"00000000";
+ out_rf_DtBuf_valid <= '0';
+
+ out_uu_DtBuf_data <= x"00000000";
+ out_uu_DtBuf_valid <= '0';
+
+ in_uu_DtBuf_request <= '0';
+ in_cr_DtBuf_request <= '0';
+ in_lf_DtBuf_request <= '0';
+ in_rf_DtBuf_request <= '0';
+ in_rr_DtBuf_request <= '0';
+
+ if (state = stt_ReconFrames) then
+ in_DtBuf_request <= out_rf_DtBuf_request;
+ out_rf_DtBuf_valid <= in_DtBuf_valid;
+ in_DtBuf_addr <= out_rf_DtBuf_addr;
+ out_rf_DtBuf_data <= in_DtBuf_data;
+
+ in_rf_DtBuf_request <= out_DtBuf_request;
+ out_DtBuf_valid <= in_rf_DtBuf_valid;
+ out_DtBuf_addr <= in_rf_DtBuf_addr;
+ out_DtBuf_data <= in_rf_DtBuf_data;
+
+ elsif (state = stt_CopyRecon) then
+ in_DtBuf_request <= out_cr_DtBuf_request;
+ out_cr_DtBuf_valid <= in_DtBuf_valid;
+ in_DtBuf_addr <= out_cr_DtBuf_addr;
+ out_cr_DtBuf_data <= in_DtBuf_data;
+
+ in_cr_DtBuf_request <= out_DtBuf_request;
+ out_DtBuf_valid <= in_cr_DtBuf_valid;
+ out_DtBuf_addr <= in_cr_DtBuf_addr;
+ out_DtBuf_data <= in_cr_DtBuf_data;
+
+ elsif (state = stt_LoopFilter) then
+ in_DtBuf_request <= out_lf_DtBuf_request;
+ out_lf_DtBuf_valid <= in_DtBuf_valid;
+ in_DtBuf_addr <= out_lf_DtBuf_addr;
+ out_lf_DtBuf_data <= in_DtBuf_data;
+
+ in_lf_DtBuf_request <= out_DtBuf_request;
+ out_DtBuf_valid <= in_lf_DtBuf_valid;
+ out_DtBuf_addr <= in_lf_DtBuf_addr;
+ out_DtBuf_data <= in_lf_DtBuf_data;
+
+ elsif (state = stt_UpdateUMV) then
+ in_DtBuf_request <= out_uu_DtBuf_request;
+ out_uu_DtBuf_valid <= in_DtBuf_valid;
+ in_DtBuf_addr <= out_uu_DtBuf_addr;
+ out_uu_DtBuf_data <= in_DtBuf_data;
+
+ in_uu_DtBuf_request <= out_DtBuf_request;
+ out_DtBuf_valid <= in_uu_DtBuf_valid;
+ out_DtBuf_addr <= in_uu_DtBuf_addr;
+ out_DtBuf_data <= in_uu_DtBuf_data;
+
+ elsif (state = stt_CleanBuffer) then
+
+ in_DtBuf_request <= out_rr_DtBuf_request;
+ out_rr_DtBuf_valid <= in_DtBuf_valid;
+ in_DtBuf_addr <= out_rr_DtBuf_addr;
+ out_rr_DtBuf_data <= in_DtBuf_data;
+
+ in_rr_DtBuf_request <= out_DtBuf_request;
+ out_DtBuf_valid <= in_rr_DtBuf_valid;
+ out_DtBuf_addr <= in_rr_DtBuf_addr;
+ out_DtBuf_data <= x"00000000";
+
+ else
+ in_DtBuf_request <= out_rr_DtBuf_request;
+ out_rr_DtBuf_valid <= in_DtBuf_valid;
+ in_DtBuf_addr <= out_rr_DtBuf_addr;
+ out_rr_DtBuf_data <= in_DtBuf_data;
+
+ out_DtBuf_valid <= '0';
+ out_DtBuf_addr <= x"00000";
+ out_DtBuf_data <= x"00000000";
+
+ end if;
+
+ if (Reset_n = '0') then
+ out_rr_DtBuf_data <= x"00000000";
+ out_rr_DtBuf_valid <= '0';
+
+ out_cr_DtBuf_data <= x"00000000";
+ out_cr_DtBuf_valid <= '0';
+
+ out_lf_DtBuf_data <= x"00000000";
+ out_lf_DtBuf_valid <= '0';
+
+ out_rf_DtBuf_data <= x"00000000";
+ out_rf_DtBuf_valid <= '0';
+
+ out_uu_DtBuf_data <= x"00000000";
+ out_uu_DtBuf_valid <= '0';
+
+ in_uu_DtBuf_request <= '0';
+ in_cr_DtBuf_request <= '0';
+ in_lf_DtBuf_request <= '0';
+ in_rf_DtBuf_request <= '0';
+ end if;
+ end process;
+
+
+ process(clk)
+
+ ---------------------------------------------------------------------------
+ -- Procedure that write zero in all positions of Data Buffer
+ ---------------------------------------------------------------------------
+ procedure CleanBuffer is
+ begin
+ in_rr_DtBuf_valid <= '1';
+ if (count = 0) then
+ in_rr_DtBuf_addr <= x"00000";
+ else
+ in_rr_DtBuf_addr <= in_rr_DtBuf_addr + 1;
+ end if;
+
+ if (in_rr_DtBuf_request = '1') then
+ count <= count + 1;
+ end if;
+
+ if (count = SHIFT_RIGHT(3*FrameSize,2)) then
+ state <= stt_Forward;
+ forward_state <= stt_forward_uniq_common;
+ in_rr_DtBuf_addr <= x"00000";
+ count <= 0;
+ in_rr_DtBuf_valid <= '0';
+ end if;
+
+ end CleanBuffer;
+
+
+-------------------------------------------------------------------------------
+-- Change the states syncronously
+-------------------------------------------------------------------------------
+ procedure ForwardControl is
+ begin
+ if (s_in_request = '1' and s_in_valid = '1') then
+-- assert false report "forward_state = "&forward_state_t'image(forward_state) severity note;
+ count <= 0;
+
+ if (forward_state = stt_rec_framesize) then
+ -- The first parameter is FrameType
+ FrameSize <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+
+ -- This is a hack. On FPGA when reset the module, I don't know explain
+ -- why, reads the first value as zero.
+ -- Here we are ignoring this zero value. So the first valid value is
+ -- the second one that the module reads. The problem happens on an
+ -- Altera Stratix II.
+ if (count = 0) then
+ count <= 1;
+ else
+ count <= 0;
+ forward_state <= stt_rec_height;
+ end if;
+
+
+ elsif (forward_state = stt_rec_height) then
+ video_height <= unsigned(in_data(9 downto 0));
+ forward_state <= stt_rec_width;
+
+ elsif (forward_state = stt_rec_width) then
+ video_width <= unsigned(in_data(9 downto 0));
+ count <= 0;
+ forward_state <= stt_forward_none;
+ state <= stt_CleanBuffer;
+
+
+ elsif (forward_state = stt_forward_uniq_common) then
+ -- Define the offsets
+ GoldenFrameOfs <= x"00000";
+ LastFrameReconOfs <= FrameSize;
+ ThisFrameReconOfs <= SHIFT_LEFT(FrameSize, 1);
+
+
+ ---------------------------------------------------------------------
+ -- Forward and read the unique values common for all modules
+ ---------------------------------------------------------------------
+ -- if count = 0 then and forward the pbi->HFragments value
+ ---------------------------------------------------------------------
+ -- if count = 1 then read and forward the pbi->YPlaneFragments value
+ ---------------------------------------------------------------------
+ -- if count = 2 then read and forward the pbi->YStride value
+ ---------------------------------------------------------------------
+ -- if count = 3 then read and forward the pbi->UVPlaneFragments value
+ ---------------------------------------------------------------------
+ -- if count = 4 then read and forward the pbi->UVStride value
+ ---------------------------------------------------------------------
+ -- if count = 5 then read and forward the pbi->VFragments value
+ ---------------------------------------------------------------------
+ -- if count = 6 then read and forward the pbi->ReconYDataOffset value
+ ---------------------------------------------------------------------
+ -- if count = 7 then read and forward the pbi->ReconUDataOffset value
+ ---------------------------------------------------------------------
+ -- if count = 8 then read and forward the pbi->ReconVDataOffset value
+ ---------------------------------------------------------------------
+ count <= count + 1;
+ if (count = 2) then
+ YStride <= unsigned(in_data(LG_MAX_SIZE+1 downto 0));
+
+ elsif (count = 4) then
+ UVStride <= unsigned(in_data(LG_MAX_SIZE downto 0));
+
+ elsif (count = 6) then
+ ReconYDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+
+ elsif (count = 7) then
+ ReconUDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+
+ elsif (count = 8) then
+ ReconVDataOffset <= unsigned(in_data(MEM_ADDR_WIDTH-1 downto 0));
+ forward_state <= stt_forward_uniq_cr_lf;
+ count <= 0;
+ end if;
+
+ elsif (forward_state = stt_forward_uniq_cr_lf) then
+ -- Forward the pbi->UnitFragments value to CopyRecon and LoopFilter
+ forward_state <= stt_forward_uniq_lf;
+
+ -- Verify if the pbi-UnitFragments value is some multiple of 32
+ -- because the matrix pbi->display_fragments is package
+ MaxDPFCount <= SHIFT_RIGHT(
+ unsigned(in_data(LG_MAX_SIZE*2 downto 0)), 5) + 1;
+ if (in_data(4 downto 0) = "00000") then
+ MaxDPFCount <= SHIFT_RIGHT(
+ unsigned(in_data(LG_MAX_SIZE*2 downto 0)), 5);
+ end if;
+
+
+ elsif (forward_state = stt_forward_uniq_lf) then
+ ---------------------------------------------------------------------
+ -- Forward the Matrices pbi->QThreshTable and pbi->LoopFilterLimits
+ -- to LoopFilter module
+ ---------------------------------------------------------------------
+ -- For Count = 0 to Count = 63 forward pbi->QThreshTable
+ ---------------------------------------------------------------------
+ -- For Count = 64 to Count = 79 forward pbi->LoopFilterLimits
+ ---------------------------------------------------------------------
+ count <= count + 1;
+ if (count = 79) then
+ forward_state <= stt_forward_uniq_uu;
+ count <= 0;
+ end if;
+
+ elsif (forward_state = stt_forward_uniq_uu) then
+ -- Forward the pbi->info.height value to UpdateUMV module
+ forward_state <= stt_forward_uniqperframe_rf;
+
+ elsif (forward_state = stt_forward_uniqperframe_rf) then
+ ---------------------------------------------------------------------
+ -- If Count = 0 forward to ReconFrame the QuantDispFrags that is
+ -- equal to pbi->CodedBlockIndex of the software
+ ---------------------------------------------------------------------
+ -- For Count = 1 to Count = 64 forward the
+ -- pbi->dequant_Y_coeffs matrix to ReconFrames
+ -----------------------------------------------------------
+ -- For Count = 65 to Count = 128 forward the
+ -- pbi->dequant_U_coeffs matrix to ReconFrames
+ -----------------------------------------------------------
+ -- For Count = 129 to Count = 192 forward the
+ -- pbi->dequant_V_coeffs matrix to ReconFrames
+ -----------------------------------------------------------
+ -- For Count = 193 to Count = 256 forward the
+ -- dequant_InterY_coeffs matrix to ReconFrames
+ -----------------------------------------------------------
+ -- For Count = 257 to Count = 320 forward the
+ -- dequant_InterU_coeffs matrix to ReconFrames
+ -----------------------------------------------------------
+ -- For Count = 321 to Count = 384 forward the
+ -- dequant_InterV_coeffs matrix to ReconFrames
+ count <= count + 1;
+ if (Count = 0) then
+ if (in_data(LG_MAX_SIZE*2-1 downto 0) = 0) then
+ forward_state <= stt_forward_none;
+ state <= stt_ReconFrames;
+ count <= 0;
+ FrameType <= (others => '1');
+ end if;
+ elsif (count = 384) then
+ forward_state <= stt_frametype;
+ count <= 0;
+ end if;
+
+ elsif (forward_state = stt_frametype) then
+ -- Forward and read the pbi->FrameType
+ forward_state <= stt_forward_golden_ofs_rf;
+ FrameType <= unsigned(in_data(7 downto 0));
+
+ -----------------------------------------------------------------------
+ -- The three states below is used to forward the three Data Buffer's
+ -- offsets to the modules that need these informations
+ -- The hardware is responsible for the offsets.
+ -----------------------------------------------------------------------
+ elsif (forward_state = stt_forward_golden_ofs_rf) then
+ forward_state <= stt_forward_last_ofs_rf;
+
+ elsif (forward_state = stt_forward_last_ofs_rf) then
+ forward_state <= stt_forward_this_ofs_rf;
+
+ elsif (forward_state = stt_forward_this_ofs_rf) then
+ forward_state <= stt_forward_rf;
+
+ elsif (forward_state = stt_forward_rf) then
+ -----------------------------------------------------------
+ -- Forward to ReconFrames the parameters below that are
+ -- sent for all fragments
+ -----------------------------------------------------------
+ -- For Count = 0 to Count = 63 forward the
+ -- pbi->QFragData(number of the fragment to be expanded)
+ -- matrix
+ ------------------------------------------------------------
+ -- If Count = 64 forward the
+ -- pbi->FragCodingMethod(number of the fragment to be expanded)
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 65 forward the
+ -- pbi->FragCoefEOB(number of the fragment to be expanded)
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 66 forward the
+ -- (pbi->FragMVect(number of the fragment to be expanded)).x
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 67 forward the
+ -- (pbi->FragMVect(number of the fragment to be expanded)).y
+ -- value
+ -----------------------------------------------------------
+ -- If Count = 68 forward the
+ -- (number of fragment to be expanded)
+ -----------------------------------------------------------
+ count <= count + 1;
+ if (count = 68) then
+ forward_state <= stt_forward_none;
+ state <= stt_ReconFrames;
+ count <= 0;
+ end if;
+
+ elsif (forward_state = stt_forward_dispfrag or
+ forward_state = stt_forward_dispfrag_golden) then
+-- assert false report "forward_state = "&forward_state_t'image(forward_state) severity note;
+-- assert false report "Count = "&integer'image(count) severity note;
+-- assert false report "MaxDPFCount = "&integer'image(to_integer(MaxDPFCount)) severity note;
+
+ count <= count + 1;
+ if (count = MaxDPFCount - 1) then
+ forward_state <= stt_forward_source_ofs_cr;
+ count <= 0;
+ end if;
+
+ elsif (forward_state = stt_forward_source_ofs_cr) then
+-- assert false report "forward_state = "&forward_state_t'image(forward_state) severity note;
+ forward_state <= stt_forward_dest_ofs_cr;
+
+ elsif (forward_state = stt_forward_dest_ofs_cr) then
+-- assert false report "forward_state = "&forward_state_t'image(forward_state) severity note;
+ forward_state <= stt_forward_none;
+ state <= stt_CopyRecon;
+
+ elsif (forward_state = stt_forward_lf) then
+ forward_state <= stt_forward_offset_lf;
+
+ elsif (forward_state = stt_forward_offset_lf) then
+ forward_state <= stt_forward_none;
+ state <= stt_LoopFilter;
+
+ elsif (forward_state = stt_forward_offset_uu) then
+ assert false report "Calling UU" severity note;
+ forward_state <= stt_forward_none;
+ state <= stt_UpdateUMV;
+ else
+ null;
+ end if;
+ end if;
+ end procedure ForwardControl;
+
+ procedure ReconFrames is
+ begin
+-- assert false report "out_rf_request = "&std_logic'image(out_rf_request) severity note;
+ if (rf_done = '1' and rf_eb_done = '1') then
+ assert false report "ReconFrames Concluido" severity note;
+ forward_state <= stt_forward_dispfrag;
+ state <= stt_Forward;
+ FrameOfsAux <= LastFrameReconOfs;
+ FrameOfsAuxSrc <= ThisFrameReconOfs;
+ elsif (rf_eb_done = '1') then
+ forward_state <= stt_forward_rf;
+ state <= stt_Forward;
+ count <= 0;
+ else
+ null;
+ end if;
+ end procedure ReconFrames;
+
+ procedure CopyRecon is
+ begin
+ if (cr_done = '1') then
+ assert false report "CopyRecon Concluido" severity note;
+
+ forward_state <= stt_forward_lf;
+ state <= stt_Forward;
+ CountCopies <= '0';
+ if (FrameType = KEY_FRAME and CountCopies = '0') then
+ CountCopies <= '1';
+ elsif (FrameType = KEY_FRAME and CountCopies = '1') then
+ forward_state <= stt_forward_offset_uu;
+ state <= stt_Forward;
+ else
+ null;
+ end if;
+ end if;
+ end procedure CopyRecon;
+
+ procedure LoopFilter is
+ begin
+ if (lf_done = '1') then
+ assert false report "LoopFilter Concluido" severity note;
+ forward_state <= stt_forward_offset_uu;
+ state <= stt_Forward;
+ end if;
+ end procedure LoopFilter;
+
+ procedure UpdateUMV is
+ begin
+ if (uu_done = '1') then
+ assert false report "UpdateUMV Concluido" severity note;
+ count_lines <= 0;
+ count_columns <= 0;
+ state <= stt_WriteOut;
+ plane_write_state <= stt_plane_write_Y;
+ write_state <= stt_write1;
+ forward_state <= stt_forward_none;
+ CountUpdates <= '0';
+ if (FrameType = KEY_FRAME and CountUpdates = '0') then
+ FrameOfsAux <= GoldenFrameOfs;
+ FrameOfsAuxSrc <= LastFrameReconOfs;
+ forward_state <= stt_forward_dispfrag_golden;
+ state <= stt_Forward;
+ CountUpdates <= '1';
+ end if;
+ end if;
+ end procedure UpdateUMV;
+
+ procedure WriteOut is
+ begin
+ s_out_valid <= '0';
+ if (write_state = stt_write1) then
+ write_state <= stt_write2;
+ out_rr_DtBuf_request <= '1';
+ out_rr_DtBuf_addr <= out_rr_DtBuf_addr + 1;
+
+ count_columns <= count_columns + 4;
+ case plane_write_state is
+
+ when stt_plane_write_Y =>
+ if (count_columns = 0) then
+ out_rr_DtBuf_addr <= resize(SHIFT_RIGHT(LastFrameReconOfs + ReconYDataOffset + YStride * (video_height - 1) - YStride*(count_lines), 2), MEM_ADDR_WIDTH);
+
+ elsif (count_columns = video_width - 4) then
+ count_columns <= 0;
+ count_lines <= count_lines + 1;
+ if (count_lines = video_height - 1) then
+ count_lines <= 0;
+ plane_write_state <= stt_plane_write_Cb;
+ end if;
+ end if;
+
+ when stt_plane_write_Cb =>
+ if (count_columns = 0) then
+ out_rr_DtBuf_addr <= resize(SHIFT_RIGHT(LastFrameReconOfs + ReconUDataOffset + UVStride * ((video_height/2) - 1) - UVStride*(count_lines), 2), MEM_ADDR_WIDTH);
+
+ elsif (count_columns = (video_width / 2) - 4) then
+ count_columns <= 0;
+ count_lines <= count_lines + 1;
+ if (count_lines = (video_height / 2) - 1) then
+ count_lines <= 0;
+ plane_write_state <= stt_plane_write_Cr;
+ end if;
+ end if;
+
+ when stt_plane_write_Cr =>
+ if (count_columns = 0) then
+ out_rr_DtBuf_addr <= resize(SHIFT_RIGHT(LastFrameReconOfs + ReconVDataOffset + UVStride * ((video_height/2) - 1) - UVStride*(count_lines), 2), MEM_ADDR_WIDTH);
+
+ elsif (count_columns = (video_width / 2) - 4) then
+ count_columns <= 0;
+ count_lines <= count_lines + 1;
+ if (count_lines = (video_height / 2) - 1) then
+ ---------------------------------------------------------------
+ -- Because count_columns, by construction, is always dividable by
+ -- 4, count_columns = 1 is used as a flag that indicate we have
+ -- wrote all the visible frame
+ ---------------------------------------------------------------
+ count_columns <= 1;
+ count_lines <= 0;
+ end if;
+
+ -------------------------------------------------------------------
+ -- If we have already wrote all the visible frame we are done
+ -------------------------------------------------------------------
+ elsif (count_columns = 1) then
+-- count_leo <= count_leo + 1;
+-- assert count_leo /= 2 report "Dois frames" severity FAILURE;
+ assert false report "Teste4" severity note;
+ count_columns <= 0;
+ forward_state <= stt_forward_uniqperframe_rf;
+ plane_write_state <= stt_plane_write_Y;
+ state <= stt_Forward;
+ write_state <= stt_write1;
+ out_rr_DtBuf_request <= '0';
+ end if;
+ end case;
+
+ elsif (write_state = stt_write2) then
+ if (out_rr_DtBuf_valid = '1') then
+ s_out_data <= out_rr_DtBuf_data;
+ out_rr_DtBuf_request <= '0';
+ write_state <= stt_write3;
+ end if;
+
+ else
+ s_out_valid <= '1';
+ out_data <= s_out_data;
+ if (out_requested = '1') then
+ write_state <= stt_write1;
+ out_rr_DtBuf_request <= '0';
+ end if;
+ end if;
+ end procedure WriteOut;
+
+ begin
+ if (clk'event and clk = '1') then
+ if (Reset_n = '0') then
+ rf_enable <= '1';
+ cr_enable <= '1';
+ lf_enable <= '1';
+ uu_enable <= '1';
+
+ plane_write_state <= stt_plane_write_Y;
+ write_state <= stt_write1;
+ forward_state <= stt_rec_framesize;
+ state <= stt_Forward;
+
+
+ CountCopies <= '0';
+ CountUpdates <= '0';
+ count <= 0;
+ out_data <= x"00000000";
+ s_out_data <= x"00000000";
+ s_out_valid <= '0';
+
+ out_rr_DtBuf_request <= '0';
+ else
+ case state is
+ when stt_CleanBuffer => CleanBuffer;
+ when stt_Forward => ForwardControl;
+ when stt_ReconFrames => ReconFrames;
+ when stt_CopyRecon => CopyRecon;
+ when stt_LoopFilter => LoopFilter;
+ when stt_UpdateUMV => UpdateUMV;
+ when others => WriteOut;
+ end case;
+ end if;
+ end if;
+ end process;
+
+
+end a_ReconRefFrames;
Property changes on: trunk/theora-fpga/theora_hardware/reconrefframes.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/theora_hardware.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/theora_hardware.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/theora_hardware.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,351 @@
+-------------------------------------------------------------------------------
+-- Title : Theora Hardware
+-- Project : theora-fpga
+-------------------------------------------------------------------------------
+-- File : theora_hardware.vhd
+-- Author : Leonardo de Paula Rosa Piga
+-- Company : LSC - IC - UNICAMP
+-- Last update: 2007/08/23
+-- Platform :
+-------------------------------------------------------------------------------
+-- Description: Wrapper to receive data from NIOS processor
+-------------------------------------------------------------------------------
+
+library std;
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity theora_hardware is
+
+ port (
+ clk : in std_logic;
+ clk_25Mhz : in std_logic;
+ reset_n : in std_logic; -- reset
+
+ ---------------------------------------------------------------------------
+ -- Ports of Handshake
+ ---------------------------------------------------------------------------
+ in_request : out std_logic;
+ in_valid : in std_logic; -- in_data
+ in_data : in signed(31 downto 0);
+
+ -- Remover depois
+ out_valid : out std_logic;
+ ---------------------------------------------------------------------------
+ -- Ports of video controller
+ ---------------------------------------------------------------------------
+ red : out std_logic_vector(7 downto 0); -- red component
+ green : out std_logic_vector(7 downto 0); -- green component
+ blue : out std_logic_vector(7 downto 0); -- blue component
+ line_pixel : out std_logic_vector(9 downto 0); -- compute line
+ column_pixel : out std_logic_vector(9 downto 0); -- compute column
+ m1, m2 : out std_logic; -- select dac mode
+ blank_n : out std_logic; -- dac command
+ sync_n : out std_logic; -- dac command
+ sync_t : out std_logic; -- dac command
+ video_clk : out std_logic; -- dac command
+ vga_vs : out std_logic; -- vertical sync
+ vga_hs : out std_logic -- horizontal sync
+ );
+
+end theora_hardware;
+
+architecture a_theora_hardware of theora_hardware is
+ constant DEPTH : natural := 8192; -- RGB MEMORY DEPTH
+ constant ADDR_WIDTH : natural := 13; -- RGB MEMORY ADDRESS WIDTH
+ constant DATA_WIDTH : natural := 24; -- RGB MEMORY DATA WIDTH
+
+ component interface_vga
+ generic (
+ DEPTH : natural := 8192; -- RGB MEMORY DEPTH
+ ADDR_WIDTH : natural := 13; -- RGB MEMORY ADDRESS WIDTH
+ DATA_WIDTH : natural := 24; -- RGB MEMORY DATA WIDTH
+ ZOOM : natural range 0 to 7 := 4 -- Image will be scaled to ZOOM
+ );
+
+ port(
+ video_clock : in std_logic;
+ reset_n : in std_logic; -- reset
+
+
+ ---------------------------------------------------------------------------
+ -- Ports of RGB frame memory
+ ---------------------------------------------------------------------------
+ rgb_rd_addr : out unsigned(ADDR_WIDTH-1 downto 0);
+ rgb_rd_data : in signed(DATA_WIDTH-1 downto 0);
+
+ ---------------------------------------------------------------------------
+ -- Port of RGB frame memory control access
+ ---------------------------------------------------------------------------
+ can_read_mem : in std_logic;
+
+ video_width : in unsigned(11 downto 0);
+ video_height : in unsigned(11 downto 0);
+
+ red : out std_logic_vector(7 downto 0); -- red component
+ green : out std_logic_vector(7 downto 0); -- green component
+ blue : out std_logic_vector(7 downto 0); -- blue component
+ line_pixel : out std_logic_vector(9 downto 0); -- compute line
+ column_pixel : out std_logic_vector(9 downto 0); -- compute column
+ m1, m2 : out std_logic; -- select dac mode
+ blank_n : out std_logic; -- dac command
+ sync_n : out std_logic; -- dac command
+ sync_t : out std_logic; -- dac command
+ video_clk : out std_logic; -- dac command
+ vga_vs : out std_logic; -- vertical sync
+ vga_hs : out std_logic -- horizontal sync
+ );
+
+ end component;
+
+ component YCbCr2RGB
+ generic (
+ DEPTH : natural := 8192; -- RGB MEMORY DEPTH
+ ADDR_WIDTH : natural := 13; -- RGB MEMORY ADDRESS WIDTH
+ DATA_WIDTH : natural := 24; -- RGB MEMORY DATA WIDTH
+ ZOOM : natural range 0 to 7 := 4 -- Image will be scaled to ZOOM
+ );
+
+ port (
+ Clk : in std_logic;
+ reset_n : in std_logic;
+
+ ---------------------------------------------------------------------------
+ -- Ports of Handshake
+ ---------------------------------------------------------------------------
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ ---------------------------------------------------------------------------
+ -- Ports of RGB frame memory
+ ---------------------------------------------------------------------------
+ rgb_rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rgb_rd_data : out signed(DATA_WIDTH-1 downto 0);
+
+ ---------------------------------------------------------------------------
+ -- Port of RGB frame memory control access
+ ---------------------------------------------------------------------------
+ can_read_mem : out std_logic
+ );
+ end component;
+
+ component ReconRefFrames
+ port (Clk,
+ Reset_n : in std_logic;
+
+ in_request : out std_logic;
+ in_valid : in std_logic;
+ in_data : in signed(31 downto 0);
+
+ out_requested : in std_logic;
+ out_valid : out std_logic;
+ out_data : out signed(31 downto 0)
+ );
+
+ end component;
+
+ constant ZOOM : natural := 2;
+
+ signal s_line_pixel : std_logic_vector(9 downto 0); -- compute line
+ signal s_column_pixel : std_logic_vector(9 downto 0); -- compute column
+
+ signal out_conv_requested : std_logic;
+ signal out_conv_valid : std_logic;
+ signal out_conv_data : signed(31 downto 0);
+
+ signal in_rr_request : std_logic;
+ signal in_rr_valid : std_logic;
+ signal in_rr_data : signed(31 downto 0);
+
+ signal out_rr_requested : std_logic;
+ signal out_rr_valid : std_logic;
+ signal out_rr_data : signed(31 downto 0);
+
+ type switch_state_t is (stt_switch1, stt_switch2, stt_switch3,
+ stt_switch4, stt_switch5);
+ signal switch_state : switch_state_t;
+ signal s_in_request : std_logic;
+
+ signal rgb_rd_addr : unsigned(ADDR_WIDTH-1 downto 0);
+ signal rgb_rd_data : signed(DATA_WIDTH-1 downto 0);
+
+ signal video_width : unsigned(11 downto 0);
+ signal video_height : unsigned(11 downto 0);
+
+ signal can_read_mem : std_logic;
+
+begin -- a_theora_hardware
+
+ interface_vga0: interface_vga
+ generic map (
+ DEPTH => DEPTH,
+ ADDR_WIDTH => ADDR_WIDTH,
+ DATA_WIDTH => DATA_WIDTH,
+ ZOOM => ZOOM)
+
+ port map (
+ video_clock => clk_25Mhz,
+ reset_n => reset_n,
+
+ ---------------------------------------------------------------------------
+ -- Ports of RGB frame memory
+ ---------------------------------------------------------------------------
+ rgb_rd_addr => rgb_rd_addr,
+ rgb_rd_data => rgb_rd_data,
+
+ ---------------------------------------------------------------------------
+ -- Port of RGB frame memory control access
+ ---------------------------------------------------------------------------
+ can_read_mem => can_read_mem,
+
+ video_width => video_width,
+ video_height => video_height,
+
+ ---------------------------------------------------------------------------
+ -- Ports of video controller
+ ---------------------------------------------------------------------------
+ red => red,
+ green => green,
+ blue => blue,
+ line_pixel => s_line_pixel,
+ column_pixel => s_column_pixel,
+ m1 => m1,
+ m2 => m2,
+ blank_n => blank_n,
+ sync_n => sync_n,
+ sync_t => sync_t,
+ video_clk => video_clk,
+ vga_vs => vga_vs,
+ vga_hs => vga_hs
+ );
+
+ YCbCr2RGB_0: YCbCr2RGB
+ generic map (
+ DEPTH => DEPTH,
+ ADDR_WIDTH => ADDR_WIDTH,
+ DATA_WIDTH => DATA_WIDTH,
+ ZOOM => ZOOM)
+ port map (
+ Clk => Clk,
+ reset_n => reset_n,
+
+ ---------------------------------------------------------------------------
+ -- Ports of Handshake
+ ---------------------------------------------------------------------------
+ in_request => out_conv_requested,
+ in_valid => out_conv_valid,
+ in_data => out_conv_data,
+
+ ---------------------------------------------------------------------------
+ -- Ports of RGB frame memory
+ ---------------------------------------------------------------------------
+ rgb_rd_addr => rgb_rd_addr,
+ rgb_rd_data => rgb_rd_data,
+
+ ---------------------------------------------------------------------------
+ -- Port of RGB frame memory control access
+ ---------------------------------------------------------------------------
+ can_read_mem => can_read_mem
+ );
+
+ reconrefframes0: ReconRefFrames
+ port map (
+ Clk => clk,
+ Reset_n => reset_n,
+
+ in_request => out_rr_requested,
+ in_valid => out_rr_valid,
+ in_data => out_rr_data,
+
+ out_requested => in_rr_request,
+ out_valid => in_rr_valid,
+ out_data => in_rr_data
+ );
+
+ in_request <= s_in_request;
+
+ out_rr_valid <= in_valid;
+
+ out_rr_data <= in_data;
+
+ Mux_out_conv_valid: with switch_state select
+ out_conv_valid <= in_valid when stt_switch3 | stt_switch4,
+ in_rr_valid when stt_switch5,
+ '0' when others;
+
+
+ Mux_out_conv_data: with switch_state select
+ out_conv_data <= in_data when stt_switch3 | stt_switch4,
+ in_rr_data when stt_switch5,
+ (others => '0') when others;
+
+ out_valid <= clk_25Mhz when (unsigned(s_line_pixel) < video_height * ZOOM and
+ unsigned(s_column_pixel) < video_width * ZOOM) else
+ '0';
+
+ line_pixel <= s_line_pixel;
+ column_pixel <= s_column_pixel;
+
+
+ SwitchSignalsIn: process (reset_n,
+ out_conv_requested, out_rr_requested,
+ switch_state)
+ begin -- process SwitchSignals
+
+ s_in_request <= '0';
+ in_rr_request <= '0';
+
+ if (switch_state = stt_switch3 or switch_state = stt_switch4) then
+ in_rr_request <= '0';
+ s_in_request <= out_rr_requested and out_conv_requested;
+
+ else
+ in_rr_request <= out_conv_requested;
+ s_in_request <= out_rr_requested;
+
+ end if;
+
+ end process SwitchSignalsIn;
+
+
+
+ -- purpose: Control the switch the interface_vga and ReconRefFrames ports' signals
+ -- type : sequential
+ -- inputs : clk, reset_n
+ SwitchSignalsControl: process (clk, reset_n)
+ begin -- process SwitchEntries
+ if reset_n = '0' then -- asynchronous reset (active low)
+ switch_state <= stt_switch1;
+
+ elsif clk'event and clk = '1' then -- rising clock edge
+ if (s_in_request = '1' and in_valid = '1') then
+ case switch_state is
+ -- Ignore first data
+ when stt_switch1 =>
+ switch_state <= stt_switch2;
+
+ -- FrameSize
+ when stt_switch2 =>
+ switch_state <= stt_switch3;
+
+ -- Video Height
+ when stt_switch3 =>
+ switch_state <= stt_switch4;
+ video_height <= unsigned(in_data(11 downto 0));
+
+ -- Video Width
+ when stt_switch4 =>
+ switch_state <= stt_switch5;
+ video_width <= unsigned(in_data(11 downto 0));
+
+ -- Reconrefframes parameters
+ when stt_switch5 =>
+ switch_state <= stt_switch5;
+ end case;
+ end if;
+ end if;
+ end process SwitchSignalsControl;
+
+end a_theora_hardware;
Property changes on: trunk/theora-fpga/theora_hardware/theora_hardware.vhd
___________________________________________________________________
Name: svn:executable
+ *
Added: trunk/theora-fpga/theora_hardware/tsyncram.vhd
===================================================================
--- trunk/theora-fpga/theora_hardware/tsyncram.vhd (rev 0)
+++ trunk/theora-fpga/theora_hardware/tsyncram.vhd 2007-09-16 00:18:52 UTC (rev 13828)
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity tsyncram is
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+end entity tsyncram;
+
+architecture rtl of tsyncram is
+
+ type MEM_TYPE is array(0 to DEPTH-1) of
+ signed(DATA_WIDTH-1 downto 0);
+ signal memory : MEM_TYPE;
+begin
+
+ process( clk )
+ begin
+ if ( rising_edge(clk) ) then
+ if ( wr_e = '1' ) then
+ memory( to_integer(wr_addr) ) <= wr_data;
+ end if;
+ rd_data <= memory( to_integer(rd_addr) );
+ end if;
+ end process;
+
+end rtl;
Property changes on: trunk/theora-fpga/theora_hardware/tsyncram.vhd
___________________________________________________________________
Name: svn:executable
+ *
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