[vorbis-dev] How many MIPS for Vorbis Decoder?

[Jens Prüfer]

Hello again,

>> But it only does 8 MIPS :(
>
> Yikes. That's really low. I can't actually find any MDCT or FFT references
> on TI's site... so I don't know how efficient it would be. A brief scan of
> the user guide reveals that it's also restricted to a 16 bit address space,
> but if that means 128KB, it's probably going to fit. Sounds like a lot of
> porting is required, though, if it will actually work.
>
> If you're looking for ultra-low-cost that probably rules out anything ARM
> based. (Grumble - ARM cores are great but they're always too damn
> expensive). You don't need anything as powerful (or expensive) as a
> StrongARM, but there's plenty of other microcontrollers around that might
> do the job a bit less marginally. Don't forget development time when you
> compare these things for cost :)

OK, so which device would you chose for the lowest cost solution? Since I also 
want to implement part of an IP Stack on the same chip (there is the uIP that 
fits in 40k but again I have no idea how "expensive" that implementation is 
concerning CPU cycles), it has to leave a bit of headroom when crunching on 
those DCT :)

There is the C2000 DSP/Microcontroller fusion series at TI that has about 40 
MIPS at an affordable price/1000 u. But it does not have to be TI of course!

I am so totally clueless (but that will change), I don't have any idea about 
memory usage either. You mentioned 128KB could be a hard constraint? I was 
hoping to get away cheap and just use the on board memory of the Chip. Ok, go 
ahead, call me an idiot :)

Just imagine a stand-alone IP ready device that has to decode a mono UDP 
Vorbis stream as cheap as humanly possible.

Thanks for your help!

Jens
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