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<P><FONT SIZE=2 FACE="Courier New">>-----Original Message-----</FONT>
<BR><FONT SIZE=2 FACE="Courier New">>From: EXTERN Wacker Klaus (Extern; CM-DI/ESP1)</FONT>
<BR><FONT SIZE=2 FACE="Courier New">>Sent: 06 October 2004 08:40</FONT>
<BR><FONT SIZE=2 FACE="Courier New">>To: tremor@xiph.org</FONT>
<BR><FONT SIZE=2 FACE="Courier New">>Subject: [Tremor] Tremor lowmem on TI 55x DSP</FONT>
<BR><FONT SIZE=2 FACE="Courier New">></FONT>
<BR><FONT SIZE=2 FACE="Courier New">> I try to port Tremor lowmem on TI 55x DSP. </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> I am not familiar with the 54x and actually I just started to work with</FONT>
<BR><FONT SIZE=2 FACE="Courier New">the 55x. </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> But here is a short summery </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> 55x 54x </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> 2 16bit MAC 1 17bit MAC </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> 3 data read busses 2 data read busses </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> 2 data write busses </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> 32 KW (64KB) DRAM ? </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> 64 KW (128KB) SRAM ? </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Better DMA </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Can only address words(2 bytes, can you believe this) ? </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Fast SDRAM interface ? </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Instruction cache ? </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> The ALUs seemed to be similar</FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Because of only three read data busses (stupid ) the two MACs have to</FONT>
<BR><FONT SIZE=2 FACE="Courier New">share one</FONT>
<BR><FONT SIZE=2 FACE="Courier New">> parameter (or it is a constant which is in register)</FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Therefore the two MACs do not produce the double amount of MAC operations </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Thanks for the help </FONT>
<BR><FONT SIZE=2 FACE="Courier New">> Klaus</FONT>
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<P><FONT SIZE=2 FACE="Courier New">Actually I think the double MAC with shared coefficient is a good design</FONT>
<BR><FONT SIZE=2 FACE="Courier New">idea and it'll give much the same performance as two whole MAC units. Easy</FONT>
<BR><FONT SIZE=2 FACE="Courier New">example: in stereo streams you'll be doing the same operation on two</FONT>
<BR><FONT SIZE=2 FACE="Courier New">independent arrays using the same coefficients. Less obvious example: the</FONT>
<BR><FONT SIZE=2 FACE="Courier New">real and imaginary parts of a complex multiply in a radix-2 FFT can still be</FONT>
<BR><FONT SIZE=2 FACE="Courier New">done simultaneously.</FONT>
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<P><FONT SIZE=2 FACE="Courier New">Usually I find I'm just wasting instructions doubling up coefficients in</FONT>
<BR><FONT SIZE=2 FACE="Courier New">SIMD multipliers (e.g Intel MMX/SSE). I'm guessing the TI 55x implementation</FONT>
<BR><FONT SIZE=2 FACE="Courier New">takes way less silicon and battery.</FONT>
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<P><FONT SIZE=2 FACE="Courier New">- John Ripley.</FONT>
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<P><FONT SIZE=2 FACE="Courier New">You are right,but my point was, that you do not have the choice and you can not expect always the double performance (or half the cycles)</FONT></P>
<P><FONT SIZE=2 FACE="Courier New">just because you have two MACs. </FONT>
<BR><FONT SIZE=2 FACE="Courier New">Klaus</FONT>
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