[tremor] Tremor HW (FPGA) implementation

[Jaime Andres Aranguren Cardona]

Read the docs... Their eval board uses:

1MB SRAM
4MB FLASH
32MB SRAM

Nothing too surprising, I think.

------------------------------
Jaime Andres Aranguren Cardona
CAC ImpSat/Conavi - Medellin
Tel: (4) 312-93-13

<p>-----Mensaje original-----
De: owner-tremor at xiph.org [mailto:owner-tremor at xiph.org]En nombre de
Jerry Durand
Enviado el: Martes, 29 de Julio de 2003 02:58 p.m.
Para: tremor at xiph.org
Asunto: RE: [tremor] Tremor HW (FPGA) implementation

<p>At 12:50 PM 7/29/2003, you wrote:
>If so, what did those guys at Finearch did? Check this out!
>
>http://www.finearch.com/english/index.htm

<p>Probably use a large external DRAM.

<p><p>----------
Jerry Durand
Durand Interstellar, Inc.
219 Oak Wood Way
Los Gatos, California 95032-2523  USA
tel:  +1 408 356-3886
fax:  +1 408 356-4659
web:  www.interstellar.com

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