Thank, Timothy!<div><div>I add this stages. </div><div>About RLE:</div><div>I have one more unresolved stage. Mike Melanson wrote in "VP3 Bitstream Format..." about RLE using:</div><div>"* Zigzag Ordering: After transforming and quantizing a block of samples,</div>
<div>the samples are not in an optimal order for run length encoding. Zigzag</div><div>ordering rearranges the samples to put more zeros between non-zero</div><div>samples."</div><div><br></div><div>If we pass zigzaged DCT coeffs of 1 block throw RLE, how after this stage i can separately write different AC for its AC-plane? For example after zig-zag we have this:</div>
<div>AC0 =1 AC(1..61) =0 AC62 =1</div><div>after RLE we have:</div><div>(0,1)(61,1)</div><div>How add zero-ACs coeff to AC(1..61) planes? Or i skip them in this planes and add store only non-zero coeff to plabes?</div><div>
Thanks</div><div>P.S. please give me more critique. More critique - better implementation<br><br><div class="gmail_quote">On 22 March 2011 22:00, <span dir="ltr"><<a href="mailto:theora-dev-request@xiph.org">theora-dev-request@xiph.org</a>></span> wrote:<br>
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Today's Topics:<br>
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1. FPGA encode stages flow diagram (digital design)<br>
2. Re: FPGA encode stages flow diagram (Timothy B. Terriberry)<br>
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Message: 1<br>
Date: Tue, 22 Mar 2011 20:42:59 +0300<br>
From: digital design <<a href="mailto:developer.fpga@gmail.com">developer.fpga@gmail.com</a>><br>
Subject: [theora-dev] FPGA encode stages flow diagram<br>
To: <a href="mailto:theora-dev@xiph.org">theora-dev@xiph.org</a><br>
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Good day!<br>
I create diagram of encoder process. Using it i create implementation of<br>
encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing<br>
stages?<br>
Here is blog <a href="http://developer-fpga.blogspot.com/" target="_blank">http://developer-fpga.blogspot.com/</a><br>
Here is picture of encoding stage 1<br>
<a href="https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg" target="_blank">https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg</a><br>
Here is picture of encoding stage 2<br>
<a href="https://lh5.googleusercontent.com/--1U5TaiVAEU/TYjYhW4n2OI/AAAAAAAAAow/vRFbzObFhww/s1600/stage2.jpg" target="_blank">https://lh5.googleusercontent.com/--1U5TaiVAEU/TYjYhW4n2OI/AAAAAAAAAow/vRFbzObFhww/s1600/stage2.jpg</a><br>
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Message: 2<br>
Date: Tue, 22 Mar 2011 10:51:55 -0700<br>
From: "Timothy B. Terriberry" <<a href="mailto:tterribe@xiph.org">tterribe@xiph.org</a>><br>
Subject: Re: [theora-dev] FPGA encode stages flow diagram<br>
Cc: <a href="mailto:theora-dev@xiph.org">theora-dev@xiph.org</a><br>
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> I create diagram of encoder process. Using it i create implementation of<br>
> encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing<br>
> stages?<br>
<br>
So, you're missing motion estimation/motion compensation/macro block<br>
mode decision/skip decision. These are not required for an encoder, of<br>
course, but are pretty important for getting compression that is at all<br>
reasonable. Even just the "NOMV" modes (where the motion vector is<br>
always (0,0)) are already a big improvement over all-INTRA. IIRC, this<br>
is the route the Elphel 333 FPGA encoder took. You're also missing the<br>
loop filter, though I guess if there's no motion compensation at all<br>
(not even NOMV), this isn't actually required, either.<br>
<br>
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