Hello,<br><br>First of all, I would like to say that my work that I wrote
in the other email would be to do in hardware the functions: CopyRecon,
LoopFilter and UpdateUMVBorder. These are modules that Leonardo had
made, but it wasn't ok in FPGA. When I had a chat with Leonardo we were
thinking in rewrite these module for to do this running in FPGA (to
debug in a Hardware level is much more difficult, sometime is faster
rewrite the code). But, Leonardo discovered the mistakes on ExpandBlock
and in the integration of modules in FPGA. The result is that all these
modules are running in FPGA and don't need to be rewrite.
<br><br>Current State of Theora Hardware<br><a href="http://www.students.ic.unicamp.br/~ra031198/current.JPG">http://www.students.ic.unicamp.br/~ra031198/current.JPG</a><br><br>Well, now I need to change the line of my project on GSoC. I
wrote some of tasks that are necessary to have a Hardward
implementation of Theora.<br><br>1 - Integration with a processor (Nios vs Leon)<br><a href="http://www.students.ic.unicamp.br/~ra031198/integration_processor.JPG">http://www.students.ic.unicamp.br/~ra031198/integration_processor.JPG
</a><br>We
will need to compile the initial part of Theora in a processor and
after to do a integration with the Hardware modules. For this, we will
need to choose the processor. Stratix II (FPGA Altera) have a good
support to NIOS. The alternative of a nonproprietary processor could be
the LEON, but I think it maybe demand pretty much work to do run.
<br><br>2 - To do a SDRAM controller.<br><a href="http://www.students.ic.unicamp.br/~ra031198/sdram_controller.JPG">http://www.students.ic.unicamp.br/~ra031198/sdram_controller.JPG</a><br>I think it is most important
of all the tasks, because the current theora hardware can just have a
maximum resolution of 280x210. I don't how much hard it will be to do
this. Tomorrow I will have a chat with a professor from my university
in order to discuss it.
<br><br>3 - To do a video controller.<br><a href="http://www.students.ic.unicamp.br/~ra031198/video_controller.JPG">http://www.students.ic.unicamp.br/~ra031198/video_controller.JPG</a><br>This will be a module after
the UpdateUMVBorder (function in Hardware). It will be the "player",
the module in hardware that will put the images on video. I will talk
with Leonardo, because it seems that He want to do this module.
<br><br>4 - To finish the ReconRefFrames and to do other function that is before ReconRefFrames (could be the UnPackVideo).<br><a href="http://www.students.ic.unicamp.br/~ra031198/reconrefframes1_unpackvideo.JPG">http://www.students.ic.unicamp.br/~ra031198/reconrefframes1_unpackvideo.JPG
</a><br>The
code that is before the ExpandBlock() in the ReconRefFrames isn't in
Hardware. I could to this part in Hardware and maybe to do also the
UnPackVideo.
<br>The problem with UnPackVideo is because has a lot decison (if's and else's), I think it better to do in a processor.<br>What do the function dsp_save_fpu() do? (it is betweet the UnPackVideo and ReconRefFrames)
<br><br>5 - To put the current Hardware Theora of old for new VP3 codebase.<br><br>Timothy told me about the old and new VP3 codebase, but I am a little confused.<br>I read the vp3-format.txt and I saw that theora/doc/vp3-
format.txt theora-old/doc/vp3-format.txt are the same file.<br>In
don't know If i am understanding something wrong. In the specification
of Theora, I saw the "VP3 Compatibility", but this shows the
differences between original VP3 and the Theora Specification. What are
differences between new and old VP3 codebase that timothy said to me?
is there any document that shows the differences?
<br>Felipe Portavales and Leonardo Piga used the libtheora-1.0alpha6
in the reference model of Hardware Theora. is libtheora-1.0alpha6 using
the new or old codebase?<br><br><br>So, I thinks the most important
task is the SDRAM controller, but the Integration with a processor and
video controller are also important. What do you think that would be
nice to me to do in the SOC?
<br><br>Timothy, if you prefer, tomorrow i will enter on IRC and we can discuss this.<br><br>Thanks,<br><br>André Costa<br clear="all"><br>-- <br>André Costa<br>Gerente Técnico<br>Projeto BrazilIP<br>LSC IC-UNICAMP <br><br>
Cel: + 55 13 9201 1870<br><a href="http://www.brazilip.org.br/">http://www.brazilip.org.br/</a>