[theora-dev] FPGA encode stages flow diagram

[digital design]

Thank, Timothy!
I add this stages.
About RLE:
I have one more unresolved stage. Mike Melanson wrote in "VP3 Bitstream
Format..." about RLE using:
"* Zigzag Ordering: After transforming and quantizing a block of samples,
the samples are not in an optimal order for run length encoding. Zigzag
ordering rearranges the samples to put more zeros between non-zero
samples."

If we pass zigzaged DCT coeffs of 1 block throw RLE, how after this stage i
can separately write different AC for its AC-plane? For example after
zig-zag we have this:
AC0 =1 AC(1..61) =0  AC62 =1
after RLE we have:
(0,1)(61,1)
How add zero-ACs coeff to AC(1..61) planes? Or i skip them in this planes
and add store only non-zero coeff to plabes?
Thanks
P.S. please give me more critique. More critique - better implementation

On 22 March 2011 22:00, <theora-dev-request at xiph.org> wrote:

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>   1. FPGA encode stages flow diagram (digital design)
>   2. Re: FPGA encode stages flow diagram (Timothy B. Terriberry)
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> Message: 1
> Date: Tue, 22 Mar 2011 20:42:59 +0300
> From: digital design <developer.fpga at gmail.com>
> Subject: [theora-dev] FPGA encode stages flow diagram
> To: theora-dev at xiph.org
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> Good day!
> I create diagram of encoder process. Using it i create implementation of
> encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing
> stages?
> Here is blog http://developer-fpga.blogspot.com/
> Here is picture of encoding stage 1
>
> https://lh4.googleusercontent.com/-NV8o9DG3jvE/TYjYXr-dYGI/AAAAAAAAAos/U06O-YvhSI0/s1600/stage1.jpg
> Here is picture of encoding stage 2
>
> https://lh5.googleusercontent.com/--1U5TaiVAEU/TYjYhW4n2OI/AAAAAAAAAow/vRFbzObFhww/s1600/stage2.jpg
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> Message: 2
> Date: Tue, 22 Mar 2011 10:51:55 -0700
> From: "Timothy B. Terriberry" <tterribe at xiph.org>
> Subject: Re: [theora-dev] FPGA encode stages flow diagram
> Cc: theora-dev at xiph.org
> Message-ID: <4D88E1BB.40102 at xiph.org>
> Content-Type: text/plain; charset=ISO-8859-1; format=flowed
>
> > I create diagram of encoder process. Using it i create implementation of
> > encoder in FPGA (Xilinx/Altera). Please critique it. Is there missing
> > stages?
>
> So, you're missing motion estimation/motion compensation/macro block
> mode decision/skip decision. These are not required for an encoder, of
> course, but are pretty important for getting compression that is at all
> reasonable. Even just the "NOMV" modes (where the motion vector is
> always (0,0)) are already a big improvement over all-INTRA. IIRC, this
> is the route the Elphel 333 FPGA encoder took. You're also missing the
> loop filter, though I guess if there's no motion compensation at all
> (not even NOMV), this isn't actually required, either.
>
>
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