[theora-dev] GSoC Apply, request for review

André Costa andre.lnc at gmail.com
Tue Mar 27 02:10:03 PDT 2007


I am sending my application I submitted for the GSoC. There are still some
hours left before the deadline, so if you have any remarks or a tip, I can
still update it.
thanks... i think there are some grammatical errors  =(...

== Name and Contact details ==

André Luiz Nazareth da Costa

Primary e-mail: andre.lnc at gmail.com
Secondary e-mail: andre.lnc at lsc.ic.unicamp.br
Gtalk: andre.lnc at gmail.com

== Project Title ==

Hardware implementation of Theora decoding

== Project ==

Decode a video in the Theora format requires a great power of processing. In
this way, the development of a specify hardware for it, is a viable solution
and some modules had already been made successful in hardware on SoC 2006.
The ideia is you get the FPGA with small embedded processor and to put just
the critical modules in the hardware.
Goal of my project is to give continuity to the project of the last year,
putting one or more modules in hardware and then diminishing the cpu-time
processing. This implementation will be done in VHDL and synthesized to the
Altera Stratix II FPGA.

Choosing the module

I could cite now some of the functions of Theora to do this in hardware, but
in order to choose a great module (or modules) to put it in hardware, I will
study and do a good analysis in the begin of project as part of this.
The functions that are interesting to be implemented in hardware should be
have the following features: a large cpu-time consumed, Isolated from other
functions and data-path intensive. For the first one, I will use the gprof
(GNU profiler) to do the analysis, and for the others, I will need to study
the Theora decoding process and then the goal of each function.

Testbenchs and Integration

I will extract the inputs and outputs (for a lot of test cases) of the
functions choosed in order to construct a testbench for this, because each
module will be developed and tested independently. When the individual
simulations of all modules are ok, I will integrated these in the pipeline
of decoder. One part will being decoded in the software (by a processor that
will be in the FPGA) and a other part in hardware.

== Schedule (12 weeks)  ==

1.Study of the Theora decoding process, the goal of each function, modules
that had already been implemented (to understand how I can integrate) and to
get cpu-time consumed for each function. (1 weeks)
2.In this stage, I will choose the module(s) and will study it deeping.  (1
3.Write these modules in VHDL, tesbenchs and to do the simulation. (6 weeks)
4.Synthesize and test these modules in FPGA, doing the integration and
comunication interface with software and hardware modules. (3 weeks)
5.Write the documentations of the hardware implementations, testbenchs and
integration. (1 weeks)

This times are just a estimative.

== Project outcome ==

To have at least more one critical module in hardware (it is very importante
to giving continuity of  works in hardwre implementation of Theora )

That is my goal of this application, implement at least one critical module,
however my intention for after this is ambitious (for the sort time of SoC),
that is works in order to have a complete hardware implementation of theora,
but is not impossible.

== My Background ==

My name is André Costa and I am a brazilian Computer Engeneering student. I
am 21 years old and I have been involved with software development and
electronics since I was 14, when I started to do two techincal courses
(Informatics and electro-electronic).

I love Softwares and Hardwares, I have been developing many SW and HW
projects since dynamics web sites until circuits boards for power
electronics and I have found in this area (programing in Hardware
Descripition Languages) what I always wanted: programing and work with

At University I have been worked (since dec/2004) in the design and
implementation of an MP3 decoder in hardware entirely developed by undergrad
students. I developed 6 (of 16) modules and It was validated in FPGA and
silicon CHIP!

== Why should you select me? ==

I know that the initiatives in the subject of Open Source Hardware still
very modest. But I think it is a good idea to begin to incentive more this
area and the Google Summer of Code seemed like the perfect opportunity. Open
Source has been a passion since I started reading about computers. Although
this, I must admit that I have never tried to write for a existing Open
Source project, perhaps because I find them already too big and complex and
with enough contributors. Nevertheless, it will introduce me to the Open
Source Development in a successful environment, like Xiph community. Thus,
it will be a nice opportunity to get introduced to Xiph, beyond to be a good
learning experience (hardware implementation and video decoding).

At University, I also worked in backend process of CHIP and then other
ambitious idea that wasn't cited in the project outcome is that with the
knowlegdes in backend process and Theora decoder that I will get, for the
future, I could to let the hardware core prepared to be placement and
routing in a CHIP.

Thus, I belive that I have the requiriments to finish this project
successful, and also I intend incentivate others people at univesity.

André Costa
Gerente Técnico
Projeto BrazilIP

Cel: + 55 13 9201 1870
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