[theora-dev] IDCTSlow works on a FPGA prototype test

Felipe Portavales Goldstein portavales at gmail.com
Tue Jun 13 14:49:43 PDT 2006

Good News :-)

I tested the IDCTSlow synthesized on FPGA and it works !

I made an interface to convert the IDCTSlow protocol to the Avalon BUS
protocol, and permit comunicate with the NIOS II Altera embeded

The IDCT works like a peripheral, receiving and sending data from a
software running on the NIOS Processor,

By now, the software is just a loop with a mem copy from a input array
to the IDCT peripheral address, and a read from the same address

The software sended some IDCT Input samples, and read the correct IDCT
decoded samples.

IT means that the IDCT is working correctly on the FPGA!


And the Brazil won the Croatia!!!!

Felipe Portavales <portavales at gmail.com>
Undergraduate Student - IC-UNICAMP
Computer Systems Laboratory

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