[theora-dev] What goes to Hardware ?

Ralph Giles giles at xiph.org
Sun Jul 2 18:39:15 PDT 2006

On Sun, Jul 02, 2006 at 07:10:00PM -0300, Felipe Portavales Goldstein wrote:

> Even if the hardware IDCT had no data transfer overhead,
> we could get only 7 ms (15%) less of decoding time per frame.

This is what profiles on the software implementation show too, no
individual component dominates, and particularly not the IDCT. I'm
not surprised you see something similar. Looks like getting an 
efficient implementation is going to be all about carefully measuring 
parallelism and bus latency.

> To put all ReconRefFrames routine in hardware I will need at least 3
> big buffers:
> Current Frame
> Last Frame
> Golden Frame
> On a 320x240 stream, it represent about 150 Kbyte of each buffer, so I
> will need about 500 Kbytes of memory.

Yes. Note that Andrey's encoder implementation was also bound by memory 
bandwidth; he said writing the memory controller was where he had to 
focus most of his effort.

> It is too much to use FPGA internal memory.
> So I'm planning use a external SRAM of 500Kbytes.
> SRAM data sheet: http://www.olimex.com/dev/pdf/71V416_DS_74666.pdf
> Another alternative is to use a PC100 SDRAM of 16 Mb:
> http://download.micron.com/pdf/datasheets/dram/sdram/128MbSDRAMx32.pdf
> http://www.altera.com/literature/ds/ds_sdram_ctrl.pdf

If you use the SDRAM do you think it will be possible to get to 720x480 
(or even 640x480) by the end of the summer? If there's a chance
for that I'd vote for that. A hardware decoder is most interesting at 
higher resolution, and it's unlikely anyone will want to spring for 
enough SRAM to do that.

Thanks for the benchmark; it's good to see this. Hope your exams went 


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