[Theora-dev] Re: FPGA implementation in the camera
jkintree at swbell.net
Sat Oct 30 07:28:56 PDT 2004
Thanks. I've just added http://sourceforge.net/projects/elphel/
to my list of bookmarks for theora.
On Saturday 30 October 2004 02:50 am, Andrey wrote:
> I believe the work is going OK - you may follow the progress on our
> sourceforge project page - it is one of the posted tasks there. Verilog
> code is in the CVS.
> Yes it will allow to perform real-time compression, with exactly the frame
> rate I was planning 1280x1024 at 30fps ("raw" pixel rate before Bayer-> YCbCr
> 4:2:0 conversion of 125/3~=42Mpix/sec.
> The implementation is targeted to the particular network camera - Elphel
> Model 333 (PCB shown here - http://www.elphel.com/3fhlo/10333/10333.gif).
> Camera now uses the line of Micron CMOS image sensors (1280x1024,
> 1600x1200 and 2048x1536), the implementation will handle up to 5MPix on
> this hardware.
> This code should work fine for the steady network camera but not good for
> camcorders - I'm not implementing motion compensation now.
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