[Theora-dev] implementation in hardware

[John Kintree]

Andrey Filippov reports at his sourceforge website that he is 50% of the way 
towards the implementation of ogg theora in a FPGA, and has a goal of 
reaching 100% (leaving out motion compensation) by Dec. 14, 2004.

These are some of the tasks he has completed most recently:

Added 8-point forward DCT following the algorithm suggested in Theora specs.
2004-10-31 22:17

Created 2-d IDCT according to Theora specs (16-bit registers, 16x16 - 
multiplier).
 Each IDCT pass uses one of the embedded multipliers (18x18) and run at twice 
the pixel frequency (currently at 125MHz), total 530 slices (7%).
2004-10-29 08:29

Jpeg and quicktime samples of images and video that have been taken with  
Elphel network cameras are of excellent quality.  I sent Andrey a message 
saying that I would be delighted to post an announcement at www.theora.org 
when he has a sample of 1280x1024 at 30fps in ogg theora format.

Seeing the progress that Andrey is making, I feel less of a sense of urgency 
about a port of theora to the DSP Stamp or other embedded hardware.  The 
Elphel network camera FPGA may be a proof of concept of hardware 
implementation of the theora codec.  
John
PS  Andrey's progress can be followed at:
http://sourceforge.net/pm/task.php?func=detailtask&project_task_id=106273&group_id=105686&group_project_id=38873

The jpeg and quicktime samples taken with various sensors can be seen at:
http://www.elphel.com/3fhlo/