[Theora-dev] implementation in hardware
jkintree at swbell.net
Wed Nov 3 07:57:34 PST 2004
Andrey Filippov reports at his sourceforge website that he is 50% of the way
towards the implementation of ogg theora in a FPGA, and has a goal of
reaching 100% (leaving out motion compensation) by Dec. 14, 2004.
These are some of the tasks he has completed most recently:
Added 8-point forward DCT following the algorithm suggested in Theora specs.
Created 2-d IDCT according to Theora specs (16-bit registers, 16x16 -
Each IDCT pass uses one of the embedded multipliers (18x18) and run at twice
the pixel frequency (currently at 125MHz), total 530 slices (7%).
Jpeg and quicktime samples of images and video that have been taken with
Elphel network cameras are of excellent quality. I sent Andrey a message
saying that I would be delighted to post an announcement at www.theora.org
when he has a sample of 1280x1024 at 30fps in ogg theora format.
Seeing the progress that Andrey is making, I feel less of a sense of urgency
about a port of theora to the DSP Stamp or other embedded hardware. The
Elphel network camera FPGA may be a proof of concept of hardware
implementation of the theora codec.
PS Andrey's progress can be followed at:
The jpeg and quicktime samples taken with various sensors can be seen at:
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