[Theora-dev] 80% there
jkintree at swbell.net
Thu Dec 2 07:35:38 PST 2004
Andrey posted the following update at his sourceforge web site. I'm sharing
it here because I think it is fascinating to see the progress in his FPGA
implemention of the Theora codec as it happens.
Wrote code and partially simulated compressor_two module with submodules.
It gets fixed-width (12-bits) "pre-tokens" from the frame buffer in the coded
order (buffer was written in macroblock-scan order) and applies Huffman
encoding (currently there is room for 30 tables of 80) so just a single block
RAM is used. Maximal code length is limited to 14 bits, but standard tables
have not more than 13 so it is not a problem. This module also combines
single EOB tokens if possible.
Result bit data is organized in 16-bit words to be sent out through DMA
controller. Total length is also calculated. Each frame is padded to multiple
of 32 bytes, extra 32 bytes added to simplify interfacing with ETRAX100LX
As all the frame header data will be calculated by the CPU and will never go
through FPGA there is a possibility to add 0-31 bits at the beginning of the
frame data - that will simplify combining data prepared by the CPU with that
coming from the FPGA.
With the above done I've got all the new modules (in addition to those already
running in the camera in JPEG/MJPEG mode) needed for the initial Theora
encoder implementation. Now I need to connect them all together, simulate the
whole thing, balance clock phases, apply timing constraints, and make the
hardware run. And then more bugs will come out that will need to be found and
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