<div dir="ltr"><div><div><div>Yes those instructions exist, although they're a bit slower than the basic 16x16->32 with 32-bit accumulation (SMLABB). So I'd be surprised if the function with 64 bit accumulation would run as fast as the current code. Don't know how much we care about 16-bit platforms. And accuracy should not matter.<br>
</div><br>On the other hand, a 64-bit implementation is much cleaner/shorter, which is always a good argument :-)<br></div>All in all, no strong preference from my side.<br></div>koen.<br></div><div class="gmail_extra"><br>
<br><div class="gmail_quote">On Fri, Jun 20, 2014 at 12:40 PM, Timothy B. Terriberry <span dir="ltr"><<a href="mailto:tterribe@xiph.org" target="_blank">tterribe@xiph.org</a>></span> wrote:<br><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
<div class="">KOEN VOS wrote:<br>
<blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">
current implementation is faster on a 32 or 16 bit processor. If you<br>
would find the opposite to be true (ie that a 64 bit implementation is<br>
faster on, say, a 32 bit ARM CPU) then perhaps we should reconsider.<br>
</blockquote>
<br></div>
Doesn't ARMv6 have a dual signed 16x16->32 multiply with a 64-bit accumulator (SMLALD)? Even v5E should have a single 16x16->32 with a 64-bit accumulator (SMLALBB). I would think a 64-bit version could be made pretty fast on 32-bit ARM, without even resorting to SIMD.<br>
</blockquote></div><br></div>