[xiph-commits] r3857 - liboggplay/trunk/src/liboggplay

[wiking at svn.annodex.net]

Author: wiking
Date: 2009-02-22 18:22:37 -0800 (Sun, 22 Feb 2009)
New Revision: 3857

Modified:
   liboggplay/trunk/src/liboggplay/yuv2rgb_x86.h
Log:
Fix x86_64 PIC problem in the asm code of yuv2rgb conversion: use rip register.


Modified: liboggplay/trunk/src/liboggplay/yuv2rgb_x86.h
===================================================================
--- liboggplay/trunk/src/liboggplay/yuv2rgb_x86.h	2009-02-21 12:02:46 UTC (rev 3856)
+++ liboggplay/trunk/src/liboggplay/yuv2rgb_x86.h	2009-02-23 02:22:37 UTC (rev 3857)
@@ -1,6 +1,13 @@
 #ifndef __YUV2RGB_X86_H__
 #define __YUV2RGB_X86_H__
 
+/* on x86_64 in PIC mode use RIP register */
+# if defined(PIC) && defined(__x86_64__)
+#define RIP "(%%rip)"
+# else
+#define RIP
+# endif
+
 #define emms() __asm__ __volatile ( "emms;" );
 #define MMX_MOVNTQ "movntq"
 #define SSE2_MOVNTQ "movdqu"
@@ -9,25 +16,25 @@
 	__asm__ __volatile__ (		\
 			"punpcklbw %%"#reg_type"4, %%"#reg_type"0;" 	/* mm0 = u3 u2 u1 u0 */\
 			"punpcklbw %%"#reg_type"4, %%"#reg_type"1;"	/* mm1 = v3 v2 v1 v0 */\
-			"psubsw simd_80w, %%"#reg_type"0;"		/* u -= 128 */\
-			"psubsw simd_80w, %%"#reg_type"1;"		/* v -= 128 */\
+			"psubsw simd_80w"RIP", %%"#reg_type"0;"		/* u -= 128 */\
+			"psubsw simd_80w"RIP", %%"#reg_type"1;"		/* v -= 128 */\
 			"psllw $3, %%"#reg_type"0;"			/* promote precision */\
 			"psllw $3, %%"#reg_type"1;"			/* promote precision */\
 			#mov_instr " %%"#reg_type"0, %%"#reg_type"2;"	/* mm2 = u3 u2 u1 u0 */\
 			#mov_instr " %%"#reg_type"1, %%"#reg_type"3;"	/* mm3 = v3 v2 v1 v0 */\
-			"pmulhw simd_U_green, %%"#reg_type"2;"		/* mm2 = u * u_green */\
-			"pmulhw simd_V_green, %%"#reg_type"3;"		/* mm3 = v * v_green */\
-			"pmulhw simd_U_blue, %%"#reg_type"0;"		/* mm0 = chroma_b */\
-			"pmulhw simd_V_red, %%"#reg_type"1;"		/* mm1 = chroma_r */\
+			"pmulhw simd_U_green"RIP", %%"#reg_type"2;"		/* mm2 = u * u_green */\
+			"pmulhw simd_V_green"RIP", %%"#reg_type"3;"		/* mm3 = v * v_green */\
+			"pmulhw simd_U_blue"RIP", %%"#reg_type"0;"		/* mm0 = chroma_b */\
+			"pmulhw simd_V_red"RIP", %%"#reg_type"1;"		/* mm1 = chroma_r */\
 			"paddsw %%"#reg_type"3, %%"#reg_type"2;"	/* mm2 = chroma_g */\
-			"psubusb simd_10w, %%"#reg_type"6;"		/* Y -= 16  */\
+			"psubusb simd_10w"RIP", %%"#reg_type"6;"		/* Y -= 16  */\
 			#mov_instr " %%"#reg_type"6, %%"#reg_type"7;"	/* mm7 = Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 */\
-			"pand simd_00ffw, %%"#reg_type"6;"		/* mm6 =    Y6    Y4    Y2    Y0 */\
+			"pand simd_00ffw"RIP", %%"#reg_type"6;"		/* mm6 =    Y6    Y4    Y2    Y0 */\
 			"psrlw $8, %%"#reg_type"7;"			/* mm7 =    Y7    Y5    Y3    Y1 */\
 			"psllw $3, %%"#reg_type"6;"			/* promote precision */\
 			"psllw $3, %%"#reg_type"7;"			/* promote precision */\
-			"pmulhw simd_Y_coeff, %%"#reg_type"6;"		/* mm6 = luma_rgb even */\
-			"pmulhw simd_Y_coeff, %%"#reg_type"7;"		/* mm7 = luma_rgb odd */\
+			"pmulhw simd_Y_coeff"RIP", %%"#reg_type"6;"		/* mm6 = luma_rgb even */\
+			"pmulhw simd_Y_coeff"RIP", %%"#reg_type"7;"		/* mm7 = luma_rgb odd */\
 			#mov_instr " %%"#reg_type"0, %%"#reg_type"3;"	/* mm3 = chroma_b */\
 			#mov_instr " %%"#reg_type"1, %%"#reg_type"4;"	/* mm4 = chroma_r */\
 			#mov_instr " %%"#reg_type"2, %%"#reg_type"5;"	/* mm5 = chroma_g */\
@@ -58,7 +65,7 @@
 #define OUTPUT_BGRA_32(mov_instr, reg_type, offset0, offset1, offset2) \
 	__asm__ __volatile__ (				\
 			/* r0=B, r1=R, r2=G */		\
-			#mov_instr " simd_alpha, %%"#reg_type"3;\n\t"\
+			#mov_instr " simd_alpha"RIP", %%"#reg_type"3;\n\t"\
 			#mov_instr " %%"#reg_type"0, %%"#reg_type"4;\n\t"\
 			#mov_instr " %%"#reg_type"1, %%"#reg_type"5;\n\t"\
 			"punpcklbw %%"#reg_type"2, %%"#reg_type"0;\n\t" /* GB GB GB GB low  */\
@@ -81,7 +88,7 @@
 #define OUTPUT_ARGB_32(mov_instr, reg_type, offset0, offset1, offset2) \
 	__asm__ __volatile__ (				\
 			/* r0=B, r1=R, r2=G */		\
-			#mov_instr " simd_alpha, %%"#reg_type"3;\n\t"\
+			#mov_instr " simd_alpha"RIP", %%"#reg_type"3;\n\t"\
 			#mov_instr " %%"#reg_type"3, %%"#reg_type"4;\n\t"\
 			#mov_instr " %%"#reg_type"2, %%"#reg_type"5;\n\t"\
 			"punpcklbw %%"#reg_type"0, %%"#reg_type"2;\n\t" /* BG BG BG BG low  */\
@@ -103,7 +110,7 @@
 #define OUTPUT_RGBA_32(mov_instr, reg_type, offset0, offset1, offset2) \
 	__asm__ __volatile__ (				\
 			/* r0=B, r1=R, r2=G */		\
-			#mov_instr " simd_alpha, %%"#reg_type"3;\n\t"\
+			#mov_instr " simd_alpha"RIP", %%"#reg_type"3;\n\t"\
 			#mov_instr " %%"#reg_type"1, %%"#reg_type"4;\n\t"\
 			#mov_instr " %%"#reg_type"0, %%"#reg_type"5;\n\t"\
 			"punpcklbw %%"#reg_type"2, %%"#reg_type"1;\n\t" /* GR GR GR GR low  */\