[xiph-commits] r11530 - trunk/theora-fpga/idctslow

[portavales at svn.xiph.org]

Author: portavales
Date: 2006-06-05 20:03:36 -0700 (Mon, 05 Jun 2006)
New Revision: 11530

Modified:
   trunk/theora-fpga/idctslow/idctslow.vhd
Log:
finished IDCTSlow

Modified: trunk/theora-fpga/idctslow/idctslow.vhd
===================================================================
--- trunk/theora-fpga/idctslow/idctslow.vhd	2006-06-05 23:51:06 UTC (rev 11529)
+++ trunk/theora-fpga/idctslow/idctslow.vhd	2006-06-06 03:03:36 UTC (rev 11530)
@@ -409,36 +409,35 @@
 
     
   begin
+     if(clk'event and clk = '1') then
+       if( Reset_n = '0' ) then
+         state <= readIn;
+         s_in_request <= '0';
+         count <= 0;
+         s_out_valid <= '0';
+         idct_state <= idct_st1;
 
-    
-     if( Reset_n = '0' ) then
-       state <= readIn;
-       s_in_request <= '0';
-       count <= 0;
-       s_out_valid <= '0';
-       idct_state <= idct_st1;
+         mem1_we <= '0';
+         mem1_waddr <= "000000";
+         mem1_raddr1 <= "000000";
+         mem1_raddr2 <= "000000";
+         
+         write_state <= w_st1;
 
-       mem1_we <= '0';
-       mem1_waddr <= "000000";
-       mem1_raddr1 <= "000000";
-       mem1_raddr2 <= "000000";
-       
-       write_state <= w_st1;
+         col_loop <= '0';
+         
+       else
+         mem1_we <= '0';
+         
+         case state is
+           when readIn => ReadIn;
+           when idct => Idct;
+                        --when proc => proc;
+           when writeOut => WriteOut;
 
-       col_loop <= '0';
-       
-     elsif(clk'event and clk = '1') then
-       mem1_we <= '0';
-       
-       case state is
-         when readIn => ReadIn;
-         when idct => Idct;
-         --when proc => proc;
-         when writeOut => WriteOut;
-
-         when others => ReadIn; state <= readIn;
-       end case;  
-
+           when others => ReadIn; state <= readIn;
+         end case;  
+       end if;
      end if;
   end process;