[xiph-commits] r11526 - trunk/theora-fpga/idctslow

portavales at svn.xiph.org portavales at svn.xiph.org
Mon Jun 5 13:15:28 PDT 2006


Author: portavales
Date: 2006-06-05 13:15:26 -0700 (Mon, 05 Jun 2006)
New Revision: 11526

Modified:
   trunk/theora-fpga/idctslow/idctslow.vhd
   trunk/theora-fpga/idctslow/tb_idctslow.vhd
Log:
idct working with latency 7 and 5% of logic cells

Modified: trunk/theora-fpga/idctslow/idctslow.vhd
===================================================================
--- trunk/theora-fpga/idctslow/idctslow.vhd	2006-06-05 19:35:07 UTC (rev 11525)
+++ trunk/theora-fpga/idctslow/idctslow.vhd	2006-06-05 20:15:26 UTC (rev 11526)
@@ -231,6 +231,7 @@
     procedure Idct is
       variable col : integer range 0 to 8;
       variable adjustBeforeShift : integer range 0 to 8;
+      variable wdata_aux : ogg_int_16_t;
     begin
 
       if( col_loop = '1' )then
@@ -252,22 +253,17 @@
         when rst2 =>
           idct_state <= rst3;
 
+          mem1_raddr1 <= to_unsigned(3*col + count, 6);
+          mem1_raddr2 <= to_unsigned(5*col + count, 6);
+
         when rst3 =>
-          idct_state <= rst4;
+          idct_state <= rst5;
            s_A <= "*"(xC1S7, mem1_rdata1)(31 downto 16) +
                   "*"(xC7S1, mem1_rdata2)(31 downto 16);
           
            s_B <= "*"(xC7S1, mem1_rdata1)(31 downto 16) -
                   "*"(xC1S7, mem1_rdata2)(31 downto 16);
 
-          
-          mem1_raddr1 <= to_unsigned(3*col + count, 6);
-          mem1_raddr2 <= to_unsigned(5*col + count, 6);
-
-          
-        when rst4 =>
-          idct_state <= rst5;
-
         when rst5 =>
           idct_state <= rst6;        
 
@@ -277,8 +273,11 @@
           s_D <= "*"(xC3S5, mem1_rdata2 )(31 downto 16) -
                  "*"(xC5S3, mem1_rdata1 )(31 downto 16);
 
+          mem1_raddr1 <= to_unsigned(0*col + count, 6);
+          mem1_raddr2 <= to_unsigned(4*col + count, 6);
+          
         when rst6 =>
-          idct_state <= rst7;        
+          idct_state <= rst8;        
           
           s_Ad <= "*"(xC4S4, (s_A - s_C))(31 downto 16);
 
@@ -287,26 +286,16 @@
           s_Cd <= (s_A + s_C);
           s_Dd <= (s_B + s_D);
 
-          mem1_raddr1 <= to_unsigned(0*col + count, 6);
-          mem1_raddr2 <= to_unsigned(4*col + count, 6);
+          mem1_raddr1 <= to_unsigned(2*col + count, 6);
+          mem1_raddr2 <= to_unsigned(6*col + count, 6);
 
-          
-        when rst7 =>
-          idct_state <= rst8;
-
         when rst8 =>
-          idct_state <= rst9;
+          idct_state <= rst10;
 
           s_E <= "*"(xC4S4, ( mem1_rdata1 + mem1_rdata2) )(31 downto 16);          
           s_F <= "*"(xC4S4, ( mem1_rdata1 - mem1_rdata2) )(31 downto 16);
 
-          mem1_raddr1 <= to_unsigned(2*col + count, 6);
-          mem1_raddr2 <= to_unsigned(6*col + count, 6);
 
-          
-        when rst9 =>
-          idct_state <= rst10;
-
         when rst10 =>
           idct_state <= rst11;
           
@@ -334,51 +323,51 @@
         
         when rst12 =>
           idct_state <= rst13;
-          mem1_waddr <= to_unsigned( 0+count, 6 );
-          mem1_wdata <= (s_Gd + s_Cd );
-          mem1_we <= '1';
+          mem1_waddr <= to_unsigned( 0*col + count, 6 );        
+          mem1_we <= '1';          
+          wdata_aux := (s_Gd + s_Cd );
           
         when rst13 =>
           idct_state <= rst14;
-          mem1_waddr <= to_unsigned( 7+count, 6 );
-          mem1_wdata <= (s_Gd - s_Cd );
+          mem1_waddr <= to_unsigned( 7*col + count, 6 );
           mem1_we <= '1';
-          
+          wdata_aux := (s_Gd - s_Cd );
+
         when rst14 =>
           idct_state <= rst15;
-          mem1_waddr <= to_unsigned( 1+count, 6 );
-          mem1_wdata <= (s_Add + s_Hd );
+          mem1_waddr <= to_unsigned( 1*col + count, 6 );
           mem1_we <= '1';
+          wdata_aux := (s_Add + s_Hd );
           
         when rst15 =>
           idct_state <= rst16;
-          mem1_waddr <= to_unsigned( 2+count, 6 );
-          mem1_wdata <= (s_Add - s_Hd );
+          mem1_waddr <= to_unsigned( 2*col + count, 6 );
           mem1_we <= '1';
+          wdata_aux := (s_Add - s_Hd );
           
         when rst16 =>
           idct_state <= rst17;
-          mem1_waddr <= to_unsigned( 3+count, 6 );
-          mem1_wdata <= (s_Ed + s_Dd );
+          mem1_waddr <= to_unsigned( 3*col + count, 6 );
           mem1_we <= '1';
+          wdata_aux := (s_Ed + s_Dd );
           
         when rst17 =>
           idct_state <= rst18;
-          mem1_waddr <= to_unsigned( 4+count, 6 );
-          mem1_wdata <= (s_Ed - s_Dd );
+          mem1_waddr <= to_unsigned( 4*col + count, 6 );
           mem1_we <= '1';
+          wdata_aux := (s_Ed - s_Dd );
           
         when rst18 =>
           idct_state <= rst19;
-          mem1_waddr <= to_unsigned( 5+count, 6 );
-          mem1_wdata <= (s_Fd + s_Bdd );
+          mem1_waddr <= to_unsigned( 5*col + count, 6 );
           mem1_we <= '1';
+          wdata_aux := (s_Fd + s_Bdd );
           
         when rst19 =>
           idct_state <= rst1;
-          mem1_waddr <= to_unsigned( 6+count, 6 );
-          mem1_wdata <= (s_Fd - s_Bdd );
+          mem1_waddr <= to_unsigned( 6*col + count, 6 );
           mem1_we <= '1';
+          wdata_aux := (s_Fd - s_Bdd );
           
           if( count = 56 )then
             count <= 0;
@@ -452,6 +441,13 @@
 
         when others => null;
       end case;    
+
+      if( col_loop = '1' )then
+        mem1_wdata <= shift_right( wdata_aux, 4 )(15 downto 0);
+      else
+        mem1_wdata <= wdata_aux;
+      end if;
+
     end procedure Idct;
 
 

Modified: trunk/theora-fpga/idctslow/tb_idctslow.vhd
===================================================================
--- trunk/theora-fpga/idctslow/tb_idctslow.vhd	2006-06-05 19:35:07 UTC (rev 11525)
+++ trunk/theora-fpga/idctslow/tb_idctslow.vhd	2006-06-05 20:15:26 UTC (rev 11526)
@@ -39,6 +39,10 @@
   signal in_valid : std_logic;
   signal in_data : signed(15 downto 0);
 
+
+  signal samples : integer := 0;
+  signal clock_cycles : integer := 0;
+  
 begin  -- behavior
 
   idctslow0: entity work.IDctSlow
@@ -58,9 +62,11 @@
     if (resetn = '0') then
       end_of_file <= false;
 
-    elsif clk'EVENT and clk = '1' then
+    elsif clk'EVENT and clk = '1' then      
       if ( EndFile(DataInFile) or EndFile(QuantMatInFile) ) then
 	end_of_file <= true;
+        report "Latency = "&integer'image( clock_cycles/samples )&
+          " clock cycles per data sample." severity note;
       else
 
         if( out_requested = '1' )then
@@ -89,11 +95,14 @@
   begin  -- process ReadInput
     if (resetn = '0') then
     elsif clk'EVENT and clk = '1' then
+      clock_cycles <= clock_cycles + 1;
+
       in_request <= '1' after delta;
       if( in_request = '1' and in_valid = '1' )then
         --Write(output_line, now, left, 15);
 	Write(output_line, to_integer(in_data));
 	WriteLine(OutFile, output_line);
+        samples <= samples + 1;
       end if;
     end if;
 



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