[xiph-commits] r11520 - in trunk/theora-fpga: . idctslow include
portavales at svn.xiph.org
portavales at svn.xiph.org
Sun Jun 4 16:09:38 PDT 2006
Author: portavales
Date: 2006-06-04 16:09:34 -0700 (Sun, 04 Jun 2006)
New Revision: 11520
Added:
trunk/theora-fpga/include/
trunk/theora-fpga/include/syncram.vhd
Modified:
trunk/theora-fpga/idctslow/Makefile
trunk/theora-fpga/idctslow/idctslow.vhd
Log:
trasition to syncronous ram
Modified: trunk/theora-fpga/idctslow/Makefile
===================================================================
--- trunk/theora-fpga/idctslow/Makefile 2006-06-04 18:57:20 UTC (rev 11519)
+++ trunk/theora-fpga/idctslow/Makefile 2006-06-04 23:09:34 UTC (rev 11520)
@@ -3,7 +3,8 @@
@echo "PLEASE, DO: make run"
-tb_idctslow: idctslow.vhd tb_idctslow.vhd
+tb_idctslow: idctslow.vhd tb_idctslow.vhd ../include/syncram.vhd
+ ghdl -a --ieee=synopsys ../include/syncram.vhd
ghdl -a --ieee=synopsys idctslow.vhd
ghdl -a --ieee=synopsys tb_idctslow.vhd
ghdl -e --ieee=synopsys tb_idctslow
Modified: trunk/theora-fpga/idctslow/idctslow.vhd
===================================================================
--- trunk/theora-fpga/idctslow/idctslow.vhd 2006-06-04 18:57:20 UTC (rev 11519)
+++ trunk/theora-fpga/idctslow/idctslow.vhd 2006-06-04 23:09:34 UTC (rev 11520)
@@ -37,12 +37,11 @@
type mem64_t is array (0 to 63) of ogg_int_16_t;
type mem64_32bits_t is array (0 to 63) of ogg_int_32_t;
- signal InData : mem64_t;
- signal QuantMat : mem64_t;
+ signal OutData : mem64_t;
signal IntermediateData : mem64_t;
alias ip : mem64_t is IntermediateData;
- alias op : mem64_t is InData;
+ alias op : mem64_t is OutData;
signal s_A, s_B, s_C, s_D, s_Ad, s_Bd, s_Cd, s_Dd, s_E, s_F, s_G, s_H : ogg_int_16_t;
@@ -51,19 +50,27 @@
-
-- FSMs
- type state_t is (readIn,dequant,idct_row,idct_col,proc,writeOut);
+ type state_t is (readIn,idct_row,idct_col,proc,writeOut);
signal state : state_t;
- type idct_row_state_t is (idct_row_st1, idct_row_st2, idct_row_st3, idct_row_st4);
- signal idct_row_state : idct_row_state_t;
+ type row_state_t is (row_st1, row_st2, row_st3, row_st4);
+ signal row_state : row_state_t;
- type idct_col_state_t is (idct_col_st1, idct_col_st2, idct_col_st3, idct_col_st4);
- signal idct_col_state : idct_col_state_t;
+ type col_state_t is (col0, col1, col2, col3, col4, col5, col6, col7, col8, col9, col10, col11, col12, col13, col14, col15, col16);
+ signal col_state : col_state_t;
+
+
+
+ type write_state_t is (w_st1, w_st2, w_st3, w_st4);
+ signal write_state : write_state_t;
+
+
+
+
-- Handshake
-- signal count : std_logic_vector(5 downto 0);
subtype tiny_int is integer range 0 to 63;
@@ -111,9 +118,30 @@
-- constant xC6S2 : ogg_int_16_t := "0110000111111000";
-- constant xC7S1 : ogg_int_16_t := "0011000111110001";
+
+
+
+ signal mem0_we : std_logic;
+ signal mem0_waddr : unsigned(5 downto 0) := "000000";
+ signal mem0_raddr : unsigned(5 downto 0) := "000000";
+ signal mem0_wdata : ogg_int_16_t;
+ signal mem0_rdata : ogg_int_16_t;
+
+
+
begin
+ -- mem0 = 64 x 16 bits
+ mem0 : entity work.syncram
+ generic map( DEPTH => 64, DATA_WIDTH => 16, ADDR_WIDTH => 6 )
+ port map(clk, mem0_we, mem0_waddr, mem0_wdata, mem0_raddr, mem0_rdata );
+
+
+
+
+
+
in_request <= s_in_request;
out_valid <= s_out_valid;
@@ -126,11 +154,12 @@
if( s_in_request = '1' and in_valid = '1' )then
- InData( count ) <= in_data;
- QuantMat( count ) <= in_quantmat;
+ IntermediateData( to_integer(dezigzag_index( count )) ) <=
+ "*"( in_data , in_quantmat)(15 downto 0);
+
if( count = 63 )then
- state <= dequant;
+ state <= idct_row;
s_in_request <= '0';
count <= 0;
else
@@ -144,19 +173,32 @@
procedure WriteOut is
begin
- out_data <= op( count );
- s_out_valid <= '1';
+ s_out_valid <= '0';
+ case write_state is
+ when w_st1 =>
+ write_state <= w_st2;
+ mem0_raddr <= to_unsigned(count,6);
+ when w_st2 =>
+ write_state <= w_st3;
+ when w_st3 =>
+ write_state <= w_st1;
+ out_data <= mem0_rdata;
+ --out_data <= op( count );
+ s_out_valid <= '1';
- if( out_requested = '1' )then
- if( count = 63 )then
- state <= readIn; -- on readIn state must set out_valid to 0
- count <= 0;
- else
- count <= count + 1;
- end if;
- end if;
+ if( out_requested = '1' )then
+ if( count = 63 )then
+ state <= readIn; -- on readIn state must set out_valid to 0
+ count <= 0;
+ else
+ count <= count + 1;
+ end if;
+ end if;
+ when others => null;
+ end case;
+
end procedure WriteOut;
@@ -168,23 +210,8 @@
- procedure Dequant_slow is
- begin
- IntermediateData( to_integer(dezigzag_index( count )) ) <=
- "*"(InData(count), QuantMat(count))(15 downto 0);
- if( count = 63 )then
- state <= idct_row;
- count <= 0;
- else
- count <= count + 1;
- end if;
-
- end procedure Dequant_slow;
-
-
-
@@ -192,8 +219,8 @@
-- Inverse DCT on the rows now
procedure Idct_row is
begin
- case idct_row_state is
- when idct_row_st1 =>
+ case row_state is
+ when row_st1 =>
s_A <= "*"(xC1S7, ip(1 + count))(31 downto 16) +
"*"(xC7S1, ip(7 + count))(31 downto 16);
@@ -206,8 +233,8 @@
s_D <= "*"(xC3S5, ip(5 + count))(31 downto 16) -
"*"(xC5S3, ip(3 + count))(31 downto 16);
- idct_row_state <= idct_row_st2;
- when idct_row_st2 =>
+ row_state <= row_st2;
+ when row_st2 =>
s_Ad <= "*"(xC4S4, (s_A - s_C))(31 downto 16);
s_Bd <= "*"(xC4S4, (s_B - s_D))(31 downto 16);
@@ -227,9 +254,9 @@
s_H <= "*"(xC6S2, ip(2 + count))(31 downto 16) -
"*"(xC2S6, ip(6 + count))(31 downto 16);
- idct_row_state <= idct_row_st3;
+ row_state <= row_st3;
- when idct_row_st3 =>
+ when row_st3 =>
s_Ed <= (s_E - s_G );
s_Gd <= (s_E + s_G );
@@ -239,9 +266,9 @@
s_Fd <= (s_F - s_Ad );
s_Hd <= (s_Bd + s_H );
- idct_row_state <= idct_row_st4;
+ row_state <= row_st4;
- when idct_row_st4 =>
+ when row_st4 =>
ip(0 + count) <= (s_Gd + s_Cd );
ip(7 + count) <= (s_Gd - s_Cd );
@@ -254,7 +281,7 @@
ip(5 + count) <= (s_Fd + s_Bdd );
ip(6 + count) <= (s_Fd - s_Bdd );
- idct_row_state <= idct_row_st1;
+ row_state <= row_st1;
if( count = 56 )then
count <= 0;
@@ -278,22 +305,30 @@
-- Inverse DCT on the rows now
procedure Idct_col is
begin
- case idct_col_state is
- when idct_col_st1 =>
+ case col_state is
+ when col0 =>
+ col_state <= col1;
s_A <= "*"(xC1S7, ip(1*8 + count))(31 downto 16) +
"*"(xC7S1, ip(7*8 + count))(31 downto 16);
-
+
+ when col1 =>
+ col_state <= col2;
s_B <= "*"(xC7S1, ip(1*8 + count))(31 downto 16) -
"*"(xC1S7, ip(7*8 + count))(31 downto 16);
+ when col2 =>
+ col_state <= col3;
s_C <= "*"(xC3S5, ip(3*8 + count))(31 downto 16) +
"*"(xC5S3, ip(5*8 + count))(31 downto 16);
+ when col3 =>
+ col_state <= col4;
s_D <= "*"(xC3S5, ip(5*8 + count))(31 downto 16) -
"*"(xC5S3, ip(3*8 + count))(31 downto 16);
- idct_col_state <= idct_col_st2;
- when idct_col_st2 =>
+
+ when col4 =>
+ col_state <= col5;
s_Ad <= "*"(xC4S4, (s_A - s_C))(31 downto 16);
s_Bd <= "*"(xC4S4, (s_B - s_D))(31 downto 16);
@@ -301,20 +336,25 @@
s_Cd <= (s_A + s_C);
s_Dd <= (s_B + s_D);
-
+ when col5 =>
+ col_state <= col6;
s_E <= "*"(xC4S4, (ip(0*8 + count) + ip(4*8 + count)) )(31 downto 16);
s_F <= "*"(xC4S4, (ip(0*8 + count) - ip(4*8 + count)) )(31 downto 16);
+ when col6 =>
+ col_state <= col7;
s_G <= "*"(xC2S6, ip(2*8 + count))(31 downto 16) +
"*"(xC6S2, ip(6*8 + count))(31 downto 16);
+ when col7 =>
+ col_state <= col8;
s_H <= "*"(xC6S2, ip(2*8 + count))(31 downto 16) -
"*"(xC2S6, ip(6*8 + count))(31 downto 16);
- idct_col_state <= idct_col_st3;
+ when col8 =>
+ col_state <=col9;
- when idct_col_st3 =>
s_Ed <= (s_E - s_G + 8 );
s_Gd <= (s_E + s_G + 8 );
@@ -324,23 +364,64 @@
s_Fd <= (s_F - s_Ad + 8 );
s_Hd <= (s_Bd + s_H );
- idct_col_state <= idct_col_st4;
-
- when idct_col_st4 =>
+ when col9 =>
+ col_state <= col10;
op(0*8 + count) <= shift_right( (s_Gd + s_Cd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(0*8 + count,6);
+ mem0_wdata <= shift_right( (s_Gd + s_Cd ), 4 )(15 downto 0);
+
+ when col10 =>
+ col_state <= col11;
op(7*8 + count) <= shift_right( (s_Gd - s_Cd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(7*8 + count,6);
+ mem0_wdata <= shift_right( (s_Gd - s_Cd ), 4 )(15 downto 0);
+
+ when col11 =>
+ col_state <= col12;
op(1*8 + count) <= shift_right( (s_Add + s_Hd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(1*8 + count,6);
+ mem0_wdata <= shift_right( (s_Add + s_Hd ), 4 )(15 downto 0);
+
+ when col12 =>
+ col_state <= col13;
op(2*8 + count) <= shift_right( (s_Add - s_Hd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(2*8 + count,6);
+ mem0_wdata <= shift_right( (s_Add - s_Hd ), 4 )(15 downto 0);
+ when col13 =>
+ col_state <= col14;
op(3*8 + count) <= shift_right( (s_Ed + s_Dd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(3*8 + count,6);
+ mem0_wdata <= shift_right( (s_Ed + s_Dd ), 4 )(15 downto 0);
+
+ when col14 =>
+ col_state <= col15;
op(4*8 + count) <= shift_right( (s_Ed - s_Dd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(4*8 + count,6);
+ mem0_wdata <= shift_right( (s_Ed - s_Dd ), 4 )(15 downto 0);
+ when col15 =>
+ col_state <= col16;
op(5*8 + count) <= shift_right( (s_Fd + s_Bdd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(5*8 + count,6);
+ mem0_wdata <= shift_right( (s_Fd + s_Bdd ), 4 )(15 downto 0);
+
+ when col16 =>
+ col_state <= col0;
op(6*8 + count) <= shift_right( (s_Fd - s_Bdd ), 4 )(15 downto 0);
+ mem0_we <= '1';
+ mem0_waddr <= to_unsigned(6*8 + count,6);
+ mem0_wdata <= shift_right( (s_Fd - s_Bdd ), 4 )(15 downto 0);
- idct_col_state <= idct_col_st1;
-
+
if( count = 7 )then
count <= 0;
state <= writeOut;
@@ -384,12 +465,19 @@
s_in_request <= '0';
count <= 0;
s_out_valid <= '0';
- idct_row_state <= idct_row_st1;
-
+ row_state <= row_st1;
+ col_state <= col0;
+ mem0_we <= '0';
+ mem0_raddr <= "000000";
+ mem0_waddr <= "000000";
+
+ write_state <= w_st1;
+
elsif(clk'event and clk = '1') then
+ mem0_we <= '0';
+
case state is
when readIn => ReadIn;
- when dequant => Dequant_slow;
when idct_row => Idct_row;
when idct_col => Idct_col;
-- when proc => proc;
Added: trunk/theora-fpga/include/syncram.vhd
===================================================================
--- trunk/theora-fpga/include/syncram.vhd 2006-06-04 18:57:20 UTC (rev 11519)
+++ trunk/theora-fpga/include/syncram.vhd 2006-06-04 23:09:34 UTC (rev 11520)
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity syncram is
+ generic (
+ DEPTH : positive := 64; -- How many slots
+ DATA_WIDTH : positive := 16; -- How many bits per slot
+ ADDR_WIDTH : positive := 6 -- = ceil(log2(DEPTH))
+ );
+ port (
+ clk : in std_logic;
+ wr_e : in std_logic;
+ wr_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ wr_data : in signed(DATA_WIDTH-1 downto 0);
+ rd_addr : in unsigned(ADDR_WIDTH-1 downto 0);
+ rd_data : out signed(DATA_WIDTH-1 downto 0)
+ );
+end entity syncram;
+
+architecture rtl of syncram is
+
+ type MEM_TYPE is array(0 to DEPTH-1) of
+ signed(DATA_WIDTH-1 downto 0);
+ signal memory : MEM_TYPE;
+begin
+
+ process( clk )
+ begin
+ if ( rising_edge(clk) ) then
+ if ( wr_e = '1' ) then
+ memory( to_integer(wr_addr) ) <= wr_data;
+ end if;
+ rd_data <= memory( to_integer(rd_addr) );
+ end if;
+ end process;
+
+end rtl;
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